中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

1603 records (took 0.024 seconds)

    DISTRIBUTED MULTI-DIE PROTOCOL APPLICATION INTERFACE
    51.
    发明申请
    DISTRIBUTED MULTI-DIE PROTOCOL APPLICATION INTERFACE 审中-公开

    公开(公告)号：US20190179792A1

    公开(公告)日：2019-06-13

    申请号：US16208238

    申请日：2018-12-03

    Applicant: Altera Corporation

    Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

    IPC: G06F13/42 ,  G06F5/06 ,  H04L29/06

    Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

    Differential power analysis resistant encryption and decryption functions
    52.
    发明授权
    Differential power analysis resistant encryption and decryption functions 有权

    公开(公告)号：US10320554B1

    公开(公告)日：2019-06-11

    申请号：US15139071

    申请日：2016-04-26

    Applicant: Altera Corporation

    Inventor： Bruce B. Pedersen

    IPC: H04K1/04 ,  H04L9/00 ,  H04L9/06

    Abstract: Circuits, methods, and systems are provided for securing an integrated circuit device against Differential Power Analysis (DPA) attacks. Plaintext (e.g., configuration data for a programmable device) may be encrypted in an encryption system using a cryptographic algorithm. Ciphertext may be decrypted in a decryption system using the cryptographic algorithm. The encryption and/or decryption systems may obfuscate the plaintext, the ciphertext, and/or the substitution tables used by the cryptographic algorithm. The encryption and/or decryption systems may also generate cryptographic key schedules by using different keys for encrypting/decrypting different blocks and/or by expanding round keys between encryption/decryption blocks. These techniques may help mitigate or altogether eliminate the vulnerability of cryptographic elements revealing power consumption information to learn the value of secret information, e.g., through DPA.

    HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME
    54.
    发明申请
    HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME 审中-公开

    公开(公告)号：US20190156873A1

    公开(公告)日：2019-05-23

    申请号：US16194991

    申请日：2018-11-19

    Applicant: Altera Corporation

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong ,  Lai Pheng Tan

    IPC: G11C8/04 ,  H03K19/177 ,  G06F9/4401 ,  G11C7/00 ,  G11C7/10

    Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

    Retiming with fixed power-up states
    55.
    发明授权
    Retiming with fixed power-up states 有权

    公开(公告)号：US10296701B1

    公开(公告)日：2019-05-21

    申请号：US15195837

    申请日：2016-06-28

    Applicant: ALTERA CORPORATION

    Inventor： Mahesh A. Iyer ,  Vasudeva M. Kamath ,  Robert Lawrence Walker

    IPC: G06F17/50

    Abstract: A computer-implemented method includes performing retiming using a circuit design to determine a retimed variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes maintaining fixed power-up states for the second set of registers in the variations. The fixed power-up states for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to increase the effect of retiming.

    Cross-point programming of pipelined interconnect circuitry
    56.
    发明授权
    Cross-point programming of pipelined interconnect circuitry 有权

    公开(公告)号：US10289585B1

    公开(公告)日：2019-05-14

    申请号：US14464237

    申请日：2014-08-20

    Applicant: Altera Corporation

    Inventor： Jeffrey Christopher Chromczak

    IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42

    Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in storage nodes of a pipeline element and the identical routing signal bypassing the pipeline element. A programming element may access the storage nodes of the pipeline elements for write operations and, if desired, for read operations. For example, the programming element may perform write operations to initialize the storage nodes to a known state during power-up operations or to reset the pipeline element. In addition, the programming element may perform reed operations for debug and testing purposes.

    HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT
    57.
    发明申请
    HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT 审中-公开

    公开(公告)号：US20190121783A1

    公开(公告)日：2019-04-25

    申请号：US16186248

    申请日：2018-11-09

    Applicant: Altera Corporation

    Inventor： Michael D. Hutton ,  Anargyros Krikelis

    IPC: G06F15/76 ,  G06F15/78

    Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

    Multi-Rate Transceiver Circuitry
    59.
    发明申请
    Multi-Rate Transceiver Circuitry 审中-公开

    公开(公告)号：US20190097784A1

    公开(公告)日：2019-03-28

    申请号：US16154513

    申请日：2018-10-08

    Applicant: Altera Corporation

    Inventor： Boon Hong Oh ,  Chee Sent Tan ,  Chau Perng Chin

    IPC: H04L7/00 ,  H03L7/00 ,  H04L7/033

    Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.

Patent Agency Ranking