公开(公告)号：US20170306491A1

公开(公告)日：2017-10-26

申请号：US15468758

申请日：2017-03-24

Applicant: Applied Materials, Inc.

Inventor： Qiwei LIANG ,  Adib KHAN ,  Tobin KAUFMAN-OSBORN ,  Srinivas D. NEMANI ,  Ludovic GODET

IPC: C23C16/455 ,  C23C16/46 ,  C23C16/458 ,  C23C16/505 ,  C23C16/44

CPC classification number: C23C16/45565 ,  B05D1/185 ,  B05D1/60 ,  C23C16/4405 ,  C23C16/4412 ,  C23C16/448 ,  C23C16/458 ,  C23C16/46 ,  C23C16/505

Abstract: Implementations described herein relate to apparatus and methods for self-assembled monolayer (SAM) deposition. Apparatus described herein includes processing chambers having various vapor phase delivery apparatus fluidly coupled thereto. SAM precursors may be delivered to process volumes of the chambers via various apparatus which is heated to maintain the precursors in vapor phase. In one implementation, a first ampoule or vaporizer configured to deliver a SAM precursor may be fluidly coupled to the process volume of a process chamber. A second ampoule or vaporizer configured to deliver a material different from the SAM precursor may also be fluidly coupled to the process volume of the process chamber.

公开(公告)号：US20170294348A1

公开(公告)日：2017-10-12

申请号：US15453675

申请日：2017-03-08

Applicant: APPLIED MATERIALS, INC.

Inventor： Bencherki MEBARKI ,  Srinivas D. NEMANI ,  Mehul NAIK

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76834 ,  H01L21/76883

Abstract: A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the first dielectric layer; depositing a first metal layer to fill the feature; etching the first metal layer to form a recess; depositing a second dielectric layer to fill the recess wherein the second dielectric layer is a low-k material suitable as a metal and oxygen diffusion barrier; forming a patterned mask layer atop the substrate to expose a portion of the second dielectric layer and the etch stop layer; etching the exposed portion of the second dielectric layer to a top surface of the first metal layer to form a via in the second dielectric layer; and depositing a second metal layer atop the substrate, wherein the second metal layer is connected to the first metal layer by the via.

公开(公告)号：US20170117157A1

公开(公告)日：2017-04-27

申请号：US15290005

申请日：2016-10-11

Applicant: Applied Materials, Inc.

Inventor： Erica CHEN ,  Ludovic GODET ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/76825 ,  H01L21/265 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/31155 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76828

Abstract: Implementations described herein relate to methods for forming gap fill materials. After the gap fill material is deposited and before a CMP process is performed on the gap fill material, one or more ion implantation processes are utilized to treat the deposited gap fill material. The one or more ion implantation processes include implanting a first ion species in the gap fill material using a first ion energy, and then implanting a second ion species in the gap fill material using a second ion energy that's lower than the first ion energy. The one or more ion implantation processes minimize CMP dishing and improve recess profile.

公开(公告)号：US20160053376A1

公开(公告)日：2016-02-25

申请号：US14489398

申请日：2014-09-17

Applicant: APPLIED MATERIALS, INC.

Inventor： Sang Ki NAM ,  Tae Seung CHO ,  Ludovic GODET ,  Srinivas D. NEMANI

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/50

CPC classification number: C23C16/45565 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/3244

Abstract: The present invention provides an apparatus having a plasma profile control plate disposed in a plasma processing chamber so as to locally alter plasma density to provide uniform plasma distribution across a substrate surface during processing. In one embodiment, a process kit includes a plate configured to be disposed in a plasma processing chamber, a plurality of apertures formed therethrough, the apertures configured to permit processing gases to flow through the plate, and an array of unit cells including at least one aperture formed in the plate, wherein each unit cell has an electrode assembly individually controllable relative to electrode assemblies disposed in at least two other unit cells.

Abstract translation: 本发明提供了一种装置，其具有设置在等离子体处理室中的等离子体轮廓控制板，从而局部地改变等离子体密度，以在处理期间在衬底表面上提供均匀的等离子体分布。 在一个实施例中，处理套件包括被配置为设置在等离子体处理室中的板，通过其形成的多个孔，所述孔被构造成允许处理气体流过板，以及包括至少一个 孔，其中每个单元电池具有相对于设置在至少两个其它单元电池中的电极组件可独立控制的电极组件。

公开(公告)号：US20150255243A1

公开(公告)日：2015-09-10

申请号：US14641071

申请日：2015-03-06

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Ellie Y. YIEH ,  Srinivas D. NEMANI ,  Gary E. DICKERSON ,  Svetlana B. RADOVANOV ,  Adam BRAND

IPC: H01J37/147 ,  H01J37/08 ,  H01J37/32

CPC classification number: H01J37/32091 ,  H01J37/32422 ,  H01J37/32568 ,  H01J37/32899

Abstract: Embodiments of the disclosure provide apparatus and methods for modifying a surface of a substrate using a plasma modification process. In one embodiment, a process generally includes the removal and/or redistribution of a portion of an exposed surface of the substrate by use of an energetic particle beam while the substrate is disposed within a particle beam modification apparatus. Embodiments may also provide a plasma modification process that includes one or more pre-planarization processing steps and/or one or more post-planarization processing steps that are all performed within one processing system. Some embodiments may provide an apparatus and methods for planarizing a surface of a substrate by performing all of the plasma modification processes within either the same processing chamber, the same processing system or within processing chambers found in two or more processing systems.

Abstract translation: 本公开的实施例提供了使用等离子体修饰工艺来修饰衬底的表面的装置和方法。 在一个实施方案中，方法通常包括通过使用能量粒子束来去除和/或重新分配衬底的暴露表面的一部分，同时将衬底设置在粒子束修改设备内。 实施例还可以提供等离子体修饰过程，其包括一个或多个预平面化处理步骤和/或一个或多个在一个处理系统内执行的后平面化处理步骤。 一些实施例可以提供用于通过执行在两个或更多个处理系统中找到的相同处理室，相同处理系统或处理室内的所有等离子体修饰过程来平坦化衬底表面的装置和方法。

公开(公告)号：US20150214101A1

公开(公告)日：2015-07-30

申请号：US14540577

申请日：2014-11-13

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Chia-Ling KAO ,  Sean KANG ,  Jeremiah T P PENDER ,  Srinivas D. NEMANI ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/308 ,  H01J37/32357 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract translation: 提供了用于消除双镶嵌结构中的导电层的早期暴露并用于蚀刻双镶嵌结构中的介电阻挡层的方法。 在一个实施例中，用于蚀刻设置在衬底上的电介质阻挡层的方法包括使用设置在介电体绝缘层上的硬掩模层作为蚀刻掩模来图案化设置在电介质阻挡层上的介电体绝缘层的衬底， 在去除绝缘体绝缘层未覆盖的绝缘体绝缘层之后，从基板去除硬掩模层，随后蚀刻由绝缘体绝缘层暴露的电介质阻挡层的部分介电阻挡层。

公开(公告)号：US20150079799A1

公开(公告)日：2015-03-19

申请号：US14029771

申请日：2013-09-17

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Praburam GOPALRAJA ,  Takehito KOSHIZAWA

IPC: H01L21/3065

CPC classification number: H01L21/31116 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063

Abstract: Methods for etching a dielectric barrier layer disposed on the substrate using a low temperature etching process along with a subsequent interface protection layer deposition process are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes transferring a substrate having a dielectric barrier layer disposed thereon into an etching processing chamber, performing a treatment process on the dielectric barrier layer, remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the treated dielectric barrier layer disposed on the substrate, plasma annealing the dielectric barrier layer to remove the dielectric barrier layer from the substrate, and forming an interface protection layer after the dielectric barrier is removed from the substrate.

Abstract translation: 提供了使用低温蚀刻工艺以及随后的界面保护层沉积工艺来蚀刻设置在基板上的电介质阻挡层的方法。 在一个实施例中，用于蚀刻设置在基板上的电介质阻挡层的方法包括将其上设置有介电阻挡层的基板转印到蚀刻处理室中，对介电阻挡层进行处理工艺，在蚀刻中远程产生等离子体 气体混合物供应到蚀刻处理室中以蚀刻设置在基板上的经处理的介电阻挡层，等离子体对介电阻挡层进行退火以从基板移除电介质阻挡层，并且在介电阻挡层从基板去除之后形成界面保护层 基质。

公开(公告)号：US20140263173A1

公开(公告)日：2014-09-18

申请号：US14201737

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： Craig ROSSLEE ,  Srinivas D. NEMANI ,  Dmitry LUBOMIRSKY ,  Ellie Y. YIEH

IPC: B05D3/06 ,  H01J37/30

CPC classification number: H01J37/3007 ,  C23C16/26 ,  C23C16/56 ,  H01J37/32422 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/02351 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31122

Abstract: Methods for using an electron beam treatment performed on an amorphous carbon layer to form a treated amorphous carbon layer with high etching resistance are provided. In one embodiment, a method of treating an amorphous carbon film includes providing a substrate having a material layer disposed, forming an amorphous carbon layer on the material layer, and performing an electron beam treatment process on the amorphous carbon layer.

Abstract translation: 提供了使用对无定形碳层进行电子束处理以形成具有高耐蚀刻性的处理的无定形碳层的方法。 在一个实施方案中，一种处理非晶碳膜的方法包括提供具有设置的材料层的基底，在该材料层上形成无定形碳层，并对非晶碳层进行电子束处理。

公开(公告)号：US20230377958A1

公开(公告)日：2023-11-23

申请号：US18228393

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun WONG ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76834 ,  H01L23/5329 ,  H01L21/28562 ,  H01L21/76832

Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.

公开(公告)号：US20220269179A1

公开(公告)日：2022-08-25

申请号：US17668065

申请日：2022-02-09

Applicant: Applied Materials, Inc.

Inventor： Douglas A. BUCHBERGER, JR. ,  Dmitry LUBOMIRSKY ,  John O. DUKOVIC ,  Srinivas D. NEMANI

IPC: G03F7/38

Abstract: A method and apparatus for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes is provided herein. The method and apparatus include an immersion bake head, which includes an electrode and is configured to be alternated between a hot pedestal and a cold pedestal. The immersion bake head serves as a substrate carrier and applies an electric field to the substrate. The immersion bake head additionally serves to provide and remove process fluid from the substrate using a plurality of fluid conduits.