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51.发明申请公开(公告)号：US20190044525A1
公开(公告)日：2019-02-07
申请号：US16154167
申请日：2018-10-08
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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52.发明申请公开(公告)号：US20180262201A1
公开(公告)日：2018-09-13
申请号：US15974756
申请日：2018-05-09
Applicant: Maxlinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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公开(公告)号：US10014888B2
公开(公告)日：2018-07-03
申请号：US15177018
申请日：2016-06-08
Applicant: MaxLinear, Inc.
Inventor： Amir Hadji-Abdolhamid , Sheng Ye
CPC classification number: H04B1/0475 , H03K3/01 , H03M9/00 , H04B1/7174 , H04B15/02 , H04L1/205 , H04L43/087 , H04L47/283
Abstract: Systems and methods are provided for jitter improvement in serializer-deserializer (SerDes) transmitters. One or more adjustments may be applied in SerDes transmitter circuitry to reduce jitter in a serial output of the SerDes transmitter circuitry, which may occur as a result of processing of input data. Applying the one or more adjustments may comprise use of dummy data. The dummy data may be configured to generate corresponding dummy current pulses which may in turn be used in controlling supply variations occurring during processing of the input data and/or generation of the serial output. The dummy data may be configured to generate the dummy current pulses such that they are applied along with current pulses corresponding to the input data. The dummy data may be adaptively set or adjusted based on the input data. The use of the dummy data may be selectively turned on or off.
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公开(公告)号：US09800253B2
公开(公告)日：2017-10-24
申请号：US15230735
申请日：2016-08-08
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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55.发明申请JITTER IMPROVEMENT IN SERIALIZER-DESERIALIZER (SERDES) TRANSMITTERS 有权SERIES-DESERIALIZER（SERDES）发射机的JITTER改进公开(公告)号：US20160359508A1
公开(公告)日：2016-12-08
申请号：US15177018
申请日：2016-06-08
Applicant: MaxLinear, Inc.
Inventor： Amir Hadji-Abdolhamid , Sheng Ye
CPC classification number: H04B1/0475 , H03K3/01 , H03M9/00 , H04B1/7174 , H04B15/02 , H04L1/205
Abstract: Systems and methods are provided for jitter improvement in serializer-deserializer (SerDes) transmitters. One or more adjustments may be applied in SerDes transmitter circuitry to reduce jitter in a serial output of the SerDes transmitter circuitry, which may occur as a result of processing of input data. Applying the one or more adjustments may comprise use of dummy data. The dummy data may be configured to generate corresponding dummy current pulses which may in turn be used in controlling supply variations occurring during processing of the input data and/or generation of the serial output. The dummy data may be configured to generate the dummy current pulses such that they are applied along with current pulses corresponding to the input data. The dummy data may be adaptively set or adjusted based on the input data. The use of the dummy data may be selectively turned on or off.
Abstract translation: 提供了串行器 - 解串器（SerDes）发射机的抖动改进的系统和方法。 可以在SerDes发射机电路中应用一个或多个调整，以减少由于输入数据的处理而发生的SerDes发射机电路的串行输出中的抖动。 应用一个或多个调整可以包括使用虚拟数据。 虚拟数据可以被配置为产生相应的虚拟电流脉冲，其可以用于控制在处理输入数据期间发生的电源变化和/或产生串行输出。 伪数据可以被配置为产生虚拟电流脉冲，使得它们与对应于输入数据的电流脉冲一起被施加。 可以基于输入数据自适应地设置或调整虚拟数据。 可以选择性地打开或关闭虚拟数据的使用。
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Patent Agency Ranking
56.发明授权Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture 有权用于异步逐次逼近模数转换器（ADC）架构的方法和系统公开(公告)号：US09337859B2
公开(公告)日：2016-05-10
申请号：US14812327
申请日：2015-07-29
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.
Abstract translation: 提供了用于控制信号处理输出的方法和系统。 在信号处理电路中，通过多个量化级别搜索与模拟输入匹配的量化级别，以及当在特定时间量内搜索失败时，调整信号处理电路的输出的至少一部分。 调整包括将输出的至少部分设置为预定值。 设置输出或其部分可以包括在正常处理路径的输出和被配置用于处理搜索失败的代码生成路径的输出之间进行选择。 可以产生用于控制信号处理电路的输出的产生的定时信息。 定时信息可以用于在通过多个量化级别的搜索期间测量每周期操作时间。
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公开(公告)号：US20160020799A1
公开(公告)日：2016-01-21
申请号：US14867795
申请日：2015-09-28
Applicant: MaxLinear, Inc.
Inventor： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
CPC classification number: H04B1/26 , H03D3/007 , H03D3/008 , H03D3/009 , H03D7/14 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/165 , H03D7/166 , H03D2200/0086 , H03H11/22 , H04B1/10 , H04B1/109 , H04B1/12 , H04B1/30 , H04B15/00 , H04J1/18 , H04L27/34
Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.
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58.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) 有权非线性随机逼近寄存器（SAR）模数转换器（ADCS）的方法与系统公开(公告)号：US20150381196A1
公开(公告)日：2015-12-31
申请号：US14843445
申请日：2015-09-02
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.
Abstract translation: 提供了利用抢占位设置决定的异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统。 特别地，这样的SAR ADC可以可操作用于当发生针对每个比较步骤确定有效输出判定的故障时，将一个或多个剩余的比特设置在对应于...的码字中但不包括一个或多个重叠的冗余比特 比较步骤，到一个特定的价值。 该值可以从紧接在前的判定中确定的比特的值导出。 可以基于动态和/或适应性标准来确定故障。 可以设置标准，例如，以便确保SAR ADC的模拟输入电压与其中使用的数模转换器（DAC）的模拟输出电压之间的差异幅度在电压的重叠范围内 对应于重叠的冗余位。
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公开(公告)号：US20150318825A1
公开(公告)日：2015-11-05
申请号：US14797207
申请日：2015-07-13
Applicant: MaxLinear, Inc.
Inventor： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
CPC classification number: H04B1/26 , H03D3/007 , H03D3/008 , H03D3/009 , H03D7/14 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/165 , H03D7/166 , H03D2200/0086 , H03H11/22 , H04B1/10 , H04B1/109 , H04B1/12 , H04B1/30 , H04B15/00 , H04J1/18 , H04L27/34
Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.
Abstract translation: 本文公开了采用谐波抑制混频器处理谐波丰富输入信号的接收机架构和方法。 所公开的接收机，混频器和方法使得接收机能够实现切换混频器的优点，同时大大降低了混频器对不需要的谐波的响应。 谐波混频器可以包括耦合到输入信号的多个混频器。 可以从单个本地振荡器输出产生本地振荡器信号的多个相位。 每个相都可用于驱动混合器之一的输入。 混频器输出可以组合以产生具有谐波抑制的频率转换输出。
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公开(公告)号：US09166606B2
公开(公告)日：2015-10-20
申请号：US14452204
申请日：2014-08-05
Applicant: MaxLinear, Inc.
Inventor： Sheng Ye
CPC classification number: H03L7/093 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/18 , H03L2207/10
Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.
Abstract translation: 锁相环可以用于利用倍频器产生频率为晶体时钟信号频率的两倍的参考时钟信号，并被键入晶体时钟信号的上升沿和下降沿。 基于生成的参考时钟信号，锁相环可以使得能够使用晶体时钟信号的上升沿和下降沿。 锁相环可以基于使能来执行锁相环的操作。 基于晶体时钟信号的上升沿和下降沿，锁相环可执行相位比较功能。 通过在锁相环中利用采样环路滤波器，锁相环可以在锁相环中的电荷泵的输出处消除与晶体时钟信号的占空比误差相关的干扰。
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