公开(公告)号：US20220107756A1

公开(公告)日：2022-04-07

申请号：US17080854

申请日：2020-10-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Chun-Wei Tsao ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

公开(公告)号：US20210082522A1

公开(公告)日：2021-03-18

申请号：US16601517

申请日：2019-10-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C16/26 ,  H03M7/42 ,  G11C11/56

Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

公开(公告)号：US20200185032A1

公开(公告)日：2020-06-11

申请号：US16248812

申请日：2019-01-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G11C16/08 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26

Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.

公开(公告)号：US20200183623A1

公开(公告)日：2020-06-11

申请号：US16258693

申请日：2019-01-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G11C7/10

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.

公开(公告)号：US20200035306A1

公开(公告)日：2020-01-30

申请号：US16120313

申请日：2018-09-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Szu-Wei Chen ,  Lih Yuarn Ou ,  Hsiao-Yi Lin

IPC: G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/04

Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.

公开(公告)号：US10310941B2

公开(公告)日：2019-06-04

申请号：US15820461

申请日：2017-11-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Chih-Kang Yeh ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  H03M13/29

Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming units; writing a second data into a second physical programming units; encoding by using the first data without using the second data to generate a first encoded data; encoding by using the second data and a first sub-data of the first data to generate a second encoded data; and writing the first encoded data and the second encoded data into a third physical programming unit and a fourth physical programming unit.

公开(公告)号：US20180374543A1

公开(公告)日：2018-12-27

申请号：US15691763

申请日：2017-08-31

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen ,  Tien-Ching Wang

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52 ,  G11C16/08

Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.

公开(公告)号：US09972390B2

公开(公告)日：2018-05-15

申请号：US15361008

申请日：2016-11-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29

CPC classification number: G11C16/04 ,  G06F3/0619 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  H03M13/2957

Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.

公开(公告)号：US09947417B2

公开(公告)日：2018-04-17

申请号：US14636191

申请日：2015-03-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/34 ,  G11C16/12 ,  G11C16/26 ,  G11C16/04 ,  G11C5/04 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C16/3459 ,  G11C5/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality of memory cells of a rewritable non-volatile memory module; determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data; performing a first operation if the storage state of the data conforms with the first condition; and performing a second operation if the storage state of the data conforms with the second condition. Accordingly, the probability of misidentifying the valid data as the invalid data may be reduced.

公开(公告)号：US09891991B2

公开(公告)日：2018-02-13

申请号：US15096284

申请日：2016-04-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/458 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: programming a first memory cell in a rewritable non-volatile memory module; reading the first memory cell based on a first hard-decision voltage level to obtain first hard-bit information and perform a hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a first type memory cell, reading the first memory cell based on a second hard-decision voltage level to obtain second hard-bit information and perform another hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a second type memory cell, reading the first memory cell based on multiple second soft-decision voltage level to obtain soft-bit information and perform soft-decoding process accordingly. Therefore, a balance can be maintained between a decoding speed and a decoding success rate.