公开(公告)号：US09873137B2

公开(公告)日：2018-01-23

申请号：US14799632

申请日：2015-07-15

Applicant: HITACHI, LTD.

Inventor： Shuntaro Machida ,  Takashi Kobayashi

IPC: B06B1/02 ,  B81C1/00 ,  C09K13/00 ,  H01L21/306 ,  C23F4/00 ,  H01L29/84

CPC classification number: B06B1/0292 ,  B81C1/00158 ,  B81C1/00182 ,  B81C1/00214 ,  B81C1/00476 ,  B81C1/00531 ,  B81C1/00611 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0109 ,  C09K13/00 ,  C23F4/00 ,  H01L21/30604 ,  H01L29/84 ,  Y10T29/49156

Abstract: Disclosed is an ultrasonic transducer that is provided with: a bottom electrode; an electric connection part which is connected to the bottom electrode from the bottom of the bottom electrode; a first insulating film which is formed so as to cover the bottom electrode; a cavity which is formed on the first insulating film so as to overlap the bottom electrode when seen from above; a second insulating film which is formed so as to cover the cavity; and a top electrode which is formed on the second insulating film so as to overlap the cavity when seen from above. The electric connection part to the bottom electrode is positioned so as to not overlap the cavity when seen from above.

公开(公告)号：US09862600B2

公开(公告)日：2018-01-09

申请号：US14718152

申请日：2015-05-21

Applicant: ams International AG

Inventor： Roel Daamen ,  Hendrik Bouman ,  Kailash Vijayakumar

IPC: B81C1/00 ,  H01L23/64 ,  B81B7/00

CPC classification number: B81C1/00825 ,  B81B7/0016 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/015 ,  B81B2207/03 ,  B81C2201/0104 ,  B81C2201/0146 ,  B81C2203/0735 ,  H01L23/642

Abstract: One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.

公开(公告)号：US09782773B2

公开(公告)日：2017-10-10

申请号：US14950320

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Yann A. Astier ,  Markus Brink ,  Michael F. Lofaro ,  Joshua T. Smith

IPC: H01L21/311 ,  B01L3/00 ,  B81C1/00 ,  B24B37/04 ,  G01N27/447 ,  G01N33/487 ,  G01N30/74 ,  G01N30/60 ,  G01N30/88

CPC classification number: B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L2200/0652 ,  B01L2200/12 ,  B01L2300/0681 ,  B01L2300/0858 ,  B01L2300/0887 ,  B01L2300/0896 ,  B24B37/042 ,  B81C1/00087 ,  B81C2201/0104 ,  B81C2201/013 ,  G01N27/44791 ,  G01N30/6039 ,  G01N30/74 ,  G01N33/48721 ,  G01N2030/885

Abstract: A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

公开(公告)号：US09714473B2

公开(公告)日：2017-07-25

申请号：US14191061

申请日：2014-02-26

Applicant: Microfabrica Inc.

Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

IPC: C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  B33Y10/00 ,  B81C1/00 ,  B81C99/00 ,  C25D1/00 ,  C25D21/12 ,  H01L21/288 ,  H01L21/768

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

公开(公告)号：US20170129767A1

公开(公告)日：2017-05-11

申请号：US15411957

申请日：2017-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Tsai-Hao HUNG ,  Shih-Chi KUO ,  Tsung-Hsien LEE ,  Tao-Cheng LIU

IPC: B81B1/00 ,  B81C1/00

CPC classification number: B81B1/004 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0163 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/012 ,  B81C1/00087 ,  B81C1/00619 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2203/0118

Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

公开(公告)号：US20160340180A1

公开(公告)日：2016-11-24

申请号：US14718152

申请日：2015-05-21

Applicant: ams International AG

Inventor： Roel Daamen ,  Hendrik Bouman ,  Kailash Vijayakumar

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00825 ,  B81B7/0016 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/015 ,  B81B2207/03 ,  B81C2201/0104 ,  B81C2201/0146 ,  B81C2203/0735 ,  H01L23/642

Abstract: One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.

Abstract translation: 一个实例公开了一种芯片，包括：基板; 耦合到所述衬底的钝化层的第一侧; 具有器件高度和空腔的器件，其中第一器件表面耦合到钝化层的与钝化层的第一侧相对的第二侧; 以及耦合到钝化层的第二侧并且被配置为具有大于或等于器件高度的结构高度的一组结构。

公开(公告)号：US20160280536A1

公开(公告)日：2016-09-29

申请号：US14777778

申请日：2014-03-17

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kippei SUGITA ,  Hiroyuki HASHIMOTO

IPC: B81C1/00

CPC classification number: B81C1/00047 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0132 ,  B82Y40/00

Abstract: A hollow structure is manufactured by preparing a lower structure which includes a concave portion, depositing a sacrifice film composed of an organic film on the lower structure by a vapor deposition polymerization method to bury the concave portion with the sacrifice film, removing an unnecessary portion of the sacrifice film, forming an upper structure on the sacrifice film with the unnecessary portion removed, and forming an air gap between the lower structure and the upper structure by removing the sacrifice film.

Abstract translation: 通过制备下部结构制造中空结构，该下部结构包括凹部，通过气相沉积聚合方法在下部结构上沉积由有机膜构成的牺牲膜以用牺牲膜掩埋凹部，除去不需要的部分 牺牲膜，在牺牲膜上形成上部结构，去除不需要的部分，并且通过去除牺牲膜在下部结构和上部结构之间形成气隙。

公开(公告)号：US20160264406A1

公开(公告)日：2016-09-15

申请号：US15162994

申请日：2016-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

公开(公告)号：US20150368090A1

公开(公告)日：2015-12-24

申请号：US14837024

申请日：2015-08-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Abstract translation: 公开了微机电系统（MEMS）结构，制造方法和设计结构。 该方法包括通过在MEMS光束上方和下方排出钨材料和硅材料来形成微电子机械系统（MEMS）光束结构，以在MEMS光束上方形成上腔体，并在MEMS光束下方形成下腔体结构。

公开(公告)号：US20140231263A1

公开(公告)日：2014-08-21

申请号：US14191061

申请日：2014-02-26

Applicant: MICROFABRICA INC.

Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

IPC: C25D5/48

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

Abstract translation: 本发明的一些实施例提供了用于电化学制造多层结构（例如中尺度或微结构）的方法和装置，其具有改进的端点检测和用于在电化学制造过程中被平坦化的材料（例如层）的并行维护。 一些方法涉及在平坦化期间使用夹具，其确保材料的平面化平面平行于给定公差内的其它沉积平面。 一些方法涉及使用端点检测夹具，其相对于第一沉积层或相对于在制造过程期间形成的一些其它层，相对于衬底的初始表面确保沉积材料的精确高度。 在一些实施例中，平面化可以通过研磨发生，而其他实施例可以使用金刚石切片机。