公开(公告)号：US06651323B2

公开(公告)日：2003-11-25

申请号：US09851064

申请日：2001-05-07

Applicant: Ted B Ziemkowski

Inventor： Ted B Ziemkowski

IPC: H01R900

CPC classification number: H05K1/0209 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09781 ,  H05K2201/10166 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method for manufacturing a surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad. The method comprises a step of providing a printed wiring board having a conductive layer disposed thereon. The method further comprises a step of selecting a size and arrangement of regions of a solder pad so as to sink sufficient heat. The method also comprises removing non-selected regions of the conductive layer to produce solder pads on the surface of the printed wiring board enhanced with features that promote heat transfer to sink enough heat generated by one of the surface mount components to provide for its proper operation.

Abstract translation: 一种用于制造表面贴装焊盘的方法，其适于用作焊接到焊盘的电子部件的散热器。 该方法包括提供其上布置有导电层的印刷线路板的步骤。 该方法还包括选择焊盘的区域的尺寸和布置以便吸收足够的热量的步骤。 该方法还包括去除导电层的未选择的区域，以在印刷线路板的表面上产生焊盘，其特征在于促进热传递以吸收由一个表面安装部件产生的足够的热量以提供其适当的操作 。

公开(公告)号：US20030180011A1

公开(公告)日：2003-09-25

申请号：US10285772

申请日：2002-11-01

Inventor： Lewis B. Aronson

IPC: G02B006/42

CPC classification number: H05K1/117 ,  G02B6/43 ,  H01R12/721 ,  H01R13/6585 ,  H05K1/0216 ,  H05K2201/0373 ,  H05K2201/093 ,  H05K2201/094 ,  H05K2201/09681 ,  H05K2201/09727

Abstract: An impedance-matching electrical connection system, for use with high-frequency communication signals, includes a circuit board and a plurality of contact pads mounted on the circuit board. The contact pads are for coupling with a plurality of complementary connectors of an external electrical device. Each coupling is associated with an excess shunt capacitance. The electrical connection system further includes a plurality of inductive traces mounted on the circuit board, each of which is connected to a respective contact pad, and is associated with a compensating series inductance. Additionally, the electrical connection system includes a plurality of signal lines mounted on the circuit board, each of which is connected to a respective inductive trace. Each inductive trace is configured so that its associated compensating series inductance substantially offsets the excess shunt capacitance associated with the coupling between the contact pad connected to the inductive trace and a complementary connector.

Abstract translation: 用于高频通信信号的阻抗匹配电连接系统包括电路板和安装在电路板上的多个接触焊盘。 接触垫用于与外部电气设备的多个互补连接器耦合。 每个耦合与多余的并联电容相关联。 电连接系统还包括安装在电路板上的多个感应迹线，每个感应迹线连接到相应的接触焊盘，并与补偿串联电感相关联。 此外，电连接系统包括安装在电路板上的多条信号线，每条信号线连接到相应的电感迹线上。 每个电感迹线配置成使得其相关联的补偿串联电感基本上抵消与连接到电感迹线的接触焊盘和互补连接器之间的耦合相关联的过量分流电容。

公开(公告)号：US06612025B1

公开(公告)日：2003-09-02

申请号：US09656043

申请日：2000-09-06

Applicant: Zhong-You (Joe) Shi ,  Lakhi N. Goenka ,  Andrew Z. Glevatsky

Inventor： Zhong-You (Joe) Shi ,  Lakhi N. Goenka ,  Andrew Z. Glevatsky

IPC: H05K334

CPC classification number: H05K3/4038 ,  H05K3/062 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09581 ,  H05K2203/1438 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A method for forming connections within a multi-layer electronic circuit board 10. The method includes forming an aperture within the circuit board and selectively coating the interior surface of the aperture with a polar solder mask material that is effective to bond with solder that is selectively inserted into the aperture, thereby retaining the solder within the aperture and improving the electrical connection provided by the solder.

Abstract translation: 一种用于在多层电子电路板10内形成连接的方法。该方法包括在电路板内形成孔，并用极性焊料掩模材料选择性地涂覆孔的内表面，极性焊料掩模材料有效地与选择性地焊接 插入到孔中，从而将焊料保持在孔内并改善由焊料提供的电连接。

公开(公告)号：USRE38053E1

公开(公告)日：2003-04-01

申请号：US09801172

申请日：2001-03-05

Applicant: Tatsuo Kanezawa

Inventor： Tatsuo Kanezawa

IPC: G02F11345

CPC classification number: G02F1/13452 ,  G02F1/1345 ,  G02F2001/13456 ,  H05K1/095 ,  H05K3/245 ,  H05K3/323 ,  H05K3/361 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373

Abstract: A liquid crystal display device is provided having a plurality of electrodes in electrical communication with a conduction portion of a plurality of external wirings. An external portion is in electrical communication with the plurality of electrodes and comprises a conduction layer having a predetermined thickness, the conduction layer being arranged in a predetermined pattern on the external portion and between the external wirings and the external portion.

Abstract translation: 一种液晶显示装置，其具有与多个外部布线的导电部分电连通的多个电极。 外部部分与多个电极电连通，并且包括具有预定厚度的导电层，导电层以预定图案布置在外部部分上以及外部布线与外部部分之间。

公开(公告)号：US06472608B2

公开(公告)日：2002-10-29

申请号：US09780819

申请日：2001-02-09

Applicant: Sadao Nakayama

Inventor： Sadao Nakayama

IPC: H05K103

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2203/0594 ,  H05K2203/1178 ,  Y02P70/611 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device of the BGA configuration comprising: a wiring layer 2 arranged on a circuit substrate 1 via an insulation layer; a land metal portion 2 formed on the wiring layer 2; a solder resist 4 layered so as to cover the land metal excluding a center portion thereof and the entire surface of the circuit substrate 1; and a solder ball 5 arranged on the land metal portion defined and surrounded by the solder resist 4; wherein the land metal portion 3 has a solder ball contact surface having a groove (or a line-shaped protrusion) 7 extending continuously.

Abstract translation: 本发明提供了一种BGA结构的半导体器件，包括：经由绝缘层布置在电路基板1上的布线层2; 形成在布线层2上的接地金属部2; 以除了其中心部分和电路基板1的整个表面的方式覆盖焊盘金属的阻焊层4; 以及布置在由阻焊剂4限定和包围的焊盘金属部分上的焊球5; 其中，所述焊盘金属部3具有连续延伸的槽（或线状突起）7的焊球接触面。

公开(公告)号：US20020093361A1

公开(公告)日：2002-07-18

申请号：US10087427

申请日：2002-02-26

Inventor： Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

IPC: G01R031/02

CPC classification number: G01R1/07314 ,  H01L2924/00013 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10S438/978 ,  Y10T29/49117 ,  Y10T29/49204 ,  H01L2224/29099

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract translation: 一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组， 半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。 公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

公开(公告)号：US06407340B1

公开(公告)日：2002-06-18

申请号：US09653941

申请日：2000-09-01

Applicant: Bo Wikström ,  Lennart Olsson

Inventor： Bo Wikström ,  Lennart Olsson

IPC: H05K100

CPC classification number: H05K1/0242 ,  H01L23/367 ,  H01L23/5283 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0209 ,  H05K1/0265 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An electronics device comprising a carrier, such as a printed circuit board, a substrate or a chip, and an electric conductor on a surface of the carrier. The surface of the conductor (2) facing away from the carrier has a surface structure (3, 4; 6, 7) in the form of flanges which are defined by etched grooves.

Abstract translation: 一种电子设备，包括载体，例如印刷电路板，基底或芯片，以及载体表面上的导电体。 导体（2）的背离载体的表面具有法兰形式的由蚀刻槽形成的表面结构（3,4; 6,7）。

公开(公告)号：US06378199B1

公开(公告)日：2002-04-30

申请号：US09222988

申请日：1998-12-22

Applicant: Hiroto Yoshinuma ,  Kenzaburo Kawai ,  Shinichi Kobayashi

Inventor： Hiroto Yoshinuma ,  Kenzaburo Kawai ,  Shinichi Kobayashi

IPC: H05K336

CPC classification number: H05K3/0023 ,  H05K1/095 ,  H05K3/143 ,  H05K3/182 ,  H05K3/184 ,  H05K3/205 ,  H05K3/225 ,  H05K3/325 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/049 ,  H05K2203/0528 ,  H05K2203/0551 ,  H05K2203/0726 ,  H05K2203/107 ,  H05K2203/1105 ,  H05K2203/1115 ,  H05K2203/135 ,  H05K2203/173 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multi-layer printed-wiring board including a substrate having a plurality of wiring pattern layers sequentially transferred thereon, each wiring pattern layer containing an electrically conductive layer and an electrically insulating layer. The wiring pattern layers are attached to the substrate through an electrically insulating layer.

Abstract translation: 一种多层印刷电路板，包括具有顺序转印在其上的多个布线图案层的基板，每个布线图案层包含导电层和电绝缘层。 布线图案层通过电绝缘层附着到基板上。

公开(公告)号：US06362435B1

公开(公告)日：2002-03-26

申请号：US09467500

申请日：1999-12-20

Applicant: Joel Franklin Downey ,  John Karl Isenberg

Inventor： Joel Franklin Downey ,  John Karl Isenberg

IPC: H05K116

CPC classification number: H01L24/81 ,  H01L23/49811 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/13033 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/092 ,  H05K1/111 ,  H05K3/248 ,  H05K2201/035 ,  H05K2201/0373 ,  H05K2201/2081 ,  H05K2203/1178 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A conductor pad, formable on a substrate or a printed circuit board, for conducing the reduction of gas voids in solder when an electronic device is soldered to the conductor pad, wherein the conductor pad includes a uniform and electrically conductive base layer having an interface surface, and also includes a patterned layer formed on the interface surface of the base layer, wherein one of the base layer and the patterned layer is substantially non-wettable and the other is substantially wettable, and wherein the base layer and the patterned layer cooperatively define strips of non-wettable surface areas which extend across the interface surface of the base layer. The strips of non-wettable surface areas can be defined upon the interface surface of the base layer in various ways to thereby create various non-wettable patterns upon the base layer. Preferably, the base layer is substantially wettable, and the patterned layer is both substantially non-wettable and electrically conductive.

Abstract translation: 一种可在基板或印刷电路板上形成的导体焊盘，用于当将电子器件焊接到导体焊盘时导致焊料中的气体空隙的减少，其中导体焊盘包括具有界面表面的均匀且导电的基底层 并且还包括形成在基底层的界面表面上的图案层，其中基底层和图案化层中的一个基本上不可润湿，另一个基本上是可润湿的，并且其中基底层和图案化层协同地限定 不可润湿表面区域的条带延伸穿过基层的界面表面。 不可润湿表面区域的条可以以各种方式限定在基层的界面表面上，从而在基层上形成各种不可润湿图案。 优选地，基底层基本上是可湿润的，并且图案化层基本上是不可湿润和导电的。

公开(公告)号：US20010050574A1

公开(公告)日：2001-12-13

申请号：US09213573

申请日：1998-12-17

Inventor： SALMAN AKRAM ,  WARREN M. FARNWORTH ,  ALAN G. WOOD

IPC: G01R031/26

CPC classification number: H05K3/4007 ,  G01R1/06738 ,  G01R1/06755 ,  G01R1/07314 ,  H01L2224/05557 ,  H01L2924/10253 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H01L2924/00

Abstract: A method for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) and a method for forming an interconnect suitable for testing this type of dice are provided. The interconnect includes a substrate having contact members comprising an array of sharpened elongated projections. The sharpened projections are formed by etching (or by growing and removing an oxide) through exposed areas of a mask. A conductive layer is formed on the sharpened projections and is in electrical communication with conductive traces formed on the substrate. The conductive layer can be formed as a layer of metal, as a stack of metals including a barrier metal, as a silicide, or as a layer of polysilicon. For testing an unpackaged die, the interconnect and die are placed in a temporary carrier and biased together. The sharpened projections are adapted to penetrate the contact location on the die to a limited penetration depth to establish an ohmic connection while minimizing damage to the contact location.

Abstract translation: 提供了一种用于测试具有凸起的接触位置（例如，凸起的接合焊盘）的未封装半导体裸片的方法和用于形成适于测试这种类型的骰子的互连的方法。 互连包括具有包括锐化的细长突起阵列的接触构件的衬底。 通过掩模的暴露区域的蚀刻（或通过生长和去除氧化物）形成锐化的突起。 导电层形成在锐化的突起上并与形成在衬底上的导电迹线电连通。 导电层可以形成为金属层，作为包括阻挡金属的金属叠层，作为硅化物，或者形成为多晶硅层。 为了测试未封装的裸片，将互连和裸片放置在临时载体中并偏置在一起。 尖锐的突起适于穿透模具上的接触位置到有限的穿透深度，以建立欧姆连接，同时最小化对接触位置的损害。