公开(公告)号：US20090031561A1

公开(公告)日：2009-02-05

申请号：US11967004

申请日：2007-12-29

Applicant: Hsiao-Chun HUANG ,  Meng-Hung WU ,  Cheng-Hsien LIN

Inventor： Hsiao-Chun HUANG ,  Meng-Hung WU ,  Cheng-Hsien LIN

IPC: H05K3/02 ,  H05K3/26 ,  H05K3/36

CPC classification number: H05K3/4092 ,  H05K3/061 ,  H05K3/281 ,  H05K2201/0397 ,  H05K2201/09063 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a hollowed printed circuit board includes steps of: providing an electrically conductive layer; laminating a first dielectric layer having a first through opening defined therein on a first surface of the electrically conductive layer; forming a protecting layer on the first surface of the electrically conductive layer in the first opening; creating an electrically conductive pattern in the conductive layer; removing the protecting layer; and laminating a second dielectric layer having a second through opening defined therein on an opposite second surface of the electrically conductive layer in a manner that the first through opening is aligned with the second through opening, thereby a portion of the electrically conductive layer is exposed to exterior through the first through opening and the second through opening.

Abstract translation: 一种中空印刷电路板的制造方法，包括以下步骤：提供导电层; 层压具有限定在其中的第一通孔的第一电介质层在导电层的第一表面上; 在第一开口中的导电层的第一表面上形成保护层; 在导电层中形成导电图案; 去除保护层; 并且以使得所述第一通孔与所述第二通孔对准的方式层叠具有限定在其中的第二通孔的第二介电层，所述第二介电层在所述导电层的相对的第二表面上，从而一部分所述导电层暴露于 外部通过第一通孔和第二通孔。

公开(公告)号：US20080274654A1

公开(公告)日：2008-11-06

申请号：US12127195

申请日：2008-05-27

Applicant: Gary Yasumura ,  Joseph C. Fjelstad ,  Kevin P. Grundy ,  William F. Wiedemann ,  Matthew J. Stepovich

Inventor： Gary Yasumura ,  Joseph C. Fjelstad ,  Kevin P. Grundy ,  William F. Wiedemann ,  Matthew J. Stepovich

IPC: H01R4/48

CPC classification number: H01R13/2407 ,  H01R12/714 ,  H01R12/79 ,  H01R13/658 ,  H05K3/326 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/0979

Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.

Abstract translation: 一种电互连装置，用于在要配合的两个导电元件的端部之间建立冗余触点，产生不具有电容短截线的电互连。

公开(公告)号：US20080220202A1

公开(公告)日：2008-09-11

申请号：US12047353

申请日：2008-03-13

Applicant: Eckhard DITZEL ,  Siegfried WALTER ,  Manfred GRESCH

Inventor： Eckhard DITZEL ,  Siegfried WALTER ,  Manfred GRESCH

IPC: B32B3/00 ,  B32B37/00

CPC classification number: H05K3/0097 ,  H01L23/49861 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/0052 ,  H05K3/202 ,  H05K3/4084 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2203/1545 ,  Y10T156/1049 ,  Y10T428/24008 ,  Y10T428/24281 ,  Y10T428/24289 ,  H01L2924/00

Abstract: A method is provided for producing a laminated substrate for mounting semiconductor chips. At least respective metal and plastic structure films having respective different recurrent contours are laminated together in such a way that a material strip is obtained. The lamination is followed by perforations or cuttings, and the method includes at least one of the following steps: A. the films are structured in such a way that superposition thereof makes it possible to obtain the areas which are devoid of overlap through the total width thereof; B. the films are not laminated through the total width of the laminate in partly recurrent areas; and C. recurrent segments of the recurrent contours are bent out of the surface of the laminated strip starting from the laminate.

Abstract translation: 提供了一种用于制造用于安装半导体芯片的层叠基板的方法。 具有各自不同轮廓轮廓的至少相应的金属和塑料结构膜以获得材料条的方式层压在一起。 层叠之后是穿孔或切割，并且该方法包括以下步骤中的至少一个：A.膜以这样的方式构造，使得其叠加使得可以通过总宽度获得没有重叠的区域 的; B.在部分复发区域中，薄膜不层压在层压板的总宽度上; 并且复制轮廓的C.复发段从层压板开始从层压带的表面弯曲出来。

公开(公告)号：US20080210457A1

公开(公告)日：2008-09-04

申请号：US12000575

申请日：2007-12-13

Applicant: Hiroaki Hiratsuka ,  Hiroshi Ishikawa ,  Masaaki Tsutsumida

Inventor： Hiroaki Hiratsuka ,  Hiroshi Ishikawa ,  Masaaki Tsutsumida

IPC: H05K1/03 ,  H05K3/06

CPC classification number: H05K3/328 ,  H01L23/4985 ,  H01L24/50 ,  H01L24/86 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/351 ,  H05K1/0393 ,  H05K3/4084 ,  H05K3/4092 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/10681 ,  H05K2203/063 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A tape carrier for semiconductor device has a resin tape provided with an opening section for bonding, and a wiring lead formed on the resin tape. The wiring lead has a notched section disposed in the opening section and including a notch width WN, and a lead width WL at a position where a bonding tool contacts the wiring lead, and a ratio of the notch width WN to the lead width WL is more than 0.5 and less than 0.685. A method for making the tape carrier includes laminating the metal foil on one surface of the resin tape including the opening section for bonding, and forming the wiring lead in the metal foil by photolithography such that the wiring lead has the notched section disposed in the opening section and including the notch width WN, and the lead width WL at the position where the bonding tool contacts the wiring lead.

Abstract translation: 用于半导体器件的带载体具有设置有用于接合的开口部分的树脂带和形成在树脂带上的布线引线。 布线引线具有设置在开口部分中并且在接合工具接触布线的位置处具有切口宽度W N N和引线宽度W L L的切口部分 引线，并且切口宽度W N N与引线宽度W L的比率大于0.5且小于0.685。 制造带载体的方法包括将金属箔层压在包括用于接合的开口部分的树脂带的一个表面上，并且通过光刻法在金属箔中形成布线引线，使得布线引线具有设置在开口中的切口部分 并且包括切口宽度W N N和在接合工具与布线引线接触的位置处的引线宽度W L L。

公开(公告)号：US20080180121A1

公开(公告)日：2008-07-31

申请号：US12060753

申请日：2008-04-01

Applicant: Igor Y. Khandros ,  A. Nicholas Sporck ,  Benjamin N. Eldrdge

Inventor： Igor Y. Khandros ,  A. Nicholas Sporck ,  Benjamin N. Eldrdge

IPC: G01R1/073

CPC classification number: H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07364 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05599

Abstract: In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

Abstract translation: 在探针卡组件中，可以将一系列探针元件排列在硅空间变压器上。 硅空间变压器可以以非常紧的间距以与半导体器件的间距相当的主要触点阵列制造。 一个优选的主要接触是弹性弹簧接触。 空间变压器中的导电元件以更放松的间距被路由到第二触点。 在一个优选实施例中，第二触头适于直接连接带状电缆，带状电缆又可连接以提供与每个主触点的选择性连接。 硅空间变压器安装在固定装置中，其提供与待测试的晶片或装置的弹性连接。 可以调整该夹具以使主触头与支撑探针卡板的平面平坦化。

公开(公告)号：US20080128159A1

公开(公告)日：2008-06-05

申请号：US12010389

申请日：2008-01-24

Applicant: Koji Ito

Inventor： Koji Ito

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H01L23/4985 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0393 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0397 ,  H05K2203/0191 ,  H05K2203/1545 ,  H05K2203/175 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49204 ,  H01L2924/00

Abstract: A tape substrate includes IC lands electrically connected to pins of a driver IC (integrated circuit), circuit board terminal lands electrically connected to an external circuit board, test lands for testing the driver IC mounted on the tape substrate, and a plating terminal used for plating the land. The test lands are arranged in a matrix. The plating terminal is disposed so as to surround the IC lands, the circuit board terminal lands, and the test lands.

Abstract translation: 带状基板包括电连接到驱动器IC（集成电路）的引脚的IC焊盘，电连接到外部电路板的电路板端子焊盘，用于测试安装在带基板上的驱动器IC的测试焊盘，以及用于 电镀土地。 试验台排列成矩阵。 电镀端子被设置成围绕IC焊盘，电路板端子焊盘和测试焊盘。

公开(公告)号：US20080102688A1

公开(公告)日：2008-05-01

申请号：US11968166

申请日：2008-01-01

Applicant: CHIH-CHENG CHEN

Inventor： CHIH-CHENG CHEN

IPC: H01R11/20

CPC classification number: H01R12/62 ,  H01R12/58 ,  H01R12/65 ,  H05K1/118 ,  H05K3/0058 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/10303 ,  H05K2201/1059

Abstract: A three-dimensional connector for a coordinate input device, which provides a touch pad and a support plate under said touch pad, includes a flat conductor cable. The flat conductor cable has an end connecting with the touch pad and another end providing a plurality of conductive lines. Each of the conductive lines corresponds to and is perpendicularly penetrated with a connecting pin; said connecting pin has a head section to press-fit with said flat conductor cable, extends through a slot, which is provided at the support plate next to said touch pad, to act as a contact such that said flat conductor cable is capable of transmitting electronic signal along a direction perpendicular to said flat conductor cable. Hence, the flat conductor cable can be connected firmly without loosening so as to enhance compactness of the three-dimensional connector substantially.

Abstract translation: 用于坐标输入装置的三维连接器，其提供在所述触摸板下方的触摸板和支撑板，包括扁平导体电缆。 扁平导体电缆具有与触摸板连接的端部，另一端提供多条导线。 每个导线对应于并且垂直地穿过连接销; 所述连接销具有头部，以与所述扁平导体电缆压配合，延伸穿过设置在所述触摸板旁边的支撑板处的槽，用作接触件，使得所述扁平导体电缆能够传输 电子信号沿垂直于所述扁平导体电缆的方向。 因此，扁平导体电缆可以牢固地连接而不松动，从而基本上提高了三维连接器的紧凑性。

公开(公告)号：US20080061434A1

公开(公告)日：2008-03-13

申请号：US11852179

申请日：2007-09-07

Applicant: Ky-Hyun JUNG ,  Wha-Su SIN ,  Heui-Seog KIM ,  Sang-Jun KIM ,  Jun-Young KO

Inventor： Ky-Hyun JUNG ,  Wha-Su SIN ,  Heui-Seog KIM ,  Sang-Jun KIM ,  Jun-Young KO

IPC: H01L23/488 ,  H01K3/22

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K3/285 ,  H05K3/3452 ,  H05K3/4092 ,  H05K2201/0215 ,  H05K2201/0245 ,  H05K2201/0397 ,  H05K2201/1025 ,  Y02P70/613 ,  Y10T29/49158 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A substrate for a semiconductor package and a method of manufacturing the same are provided. More particularly, the substrate for the semiconductor package and the method for manufacturing the same include metal pieces, with some of the metal pieces having one end embedded within an insulating layer for insulating an external connection electrode of the substrate and the other end embedded within a solder. The substrate for the semiconductor package has the effects of preventing or retarding a connection failure in a solder connection portion by blocking or retarding the propagation of a crack, and allowing a solder to be easily permeated under the metal pieces and formed at a desired position.

Abstract translation: 提供一种半导体封装用基板及其制造方法。 更具体地，用于半导体封装的衬底及其制造方法包括金属片，其中一些金属片的一端嵌入绝缘层内，用于绝缘衬底的外部连接电极，另一端嵌入 焊接。 用于半导体封装的衬底具有通过阻止或延迟裂纹的传播来防止或延迟焊料连接部分中的连接故障的效果，并且允许焊料容易地渗透在金属片下方并形成在期望的位置。

公开(公告)号：US07317322B2

公开(公告)日：2008-01-08

申请号：US11243702

申请日：2005-10-05

Applicant: Warren M. Farnworth ,  Salman Akram

Inventor： Warren M. Farnworth ,  Salman Akram

IPC: G01R31/02

CPC classification number: H05K3/326 ,  G01R1/0466 ,  G01R31/2853 ,  H05K1/118 ,  H05K3/4092 ,  H05K2201/0373 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09081 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract translation: 用于测试半导体部件的互连件包括基板和基板上的触点，用于与部件上的凸起触点进行临时电连接。 每个接触件包括一个凹部和悬在该凹部上的引线图案，其构造成电接合凸起的触点。 引线适于在凹部内在z方向上移动以适应凸起接触件的高度和平面度的变化。 此外，引线可以包括用于穿透凸起的触点的突起，用于防止与凸起的触点接合的非结合外层以及与凸起的触点的形状相匹配的弯曲形状。 可以通过在基板上形成图案化的金属层，通过将聚合物基板与其上的引线附接到基板上，或者蚀刻基板以形成导电梁来形成引线。

公开(公告)号：US07290332B1

公开(公告)日：2007-11-06

申请号：US10931371

申请日：2004-08-31

Applicant: Robert P. Howell

Inventor： Robert P. Howell

IPC: H01K3/10

CPC classification number: H05K3/326 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01R12/52 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/0307 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: According to one aspect of the present invention, a method of constructing an interposer is provided. A conductive layer is formed on a nonconductive layer. The conductive layer has via portions, non-via portions, and first and second opposing surfaces. The first surface of the conductive layer is adjacent to the nonconductive layer. Portions of the nonconductive layer are removed to expose portions of the first surface of the conductive layer. Conductive pads are formed on the exposed portions of the first surface and the second surface of the conductive layer. The non-via portions of the conductive layer are removed to form a plurality of electrically separated conductors. Each conductor includes at least two conductive pads and a via portion of the conductive layer.

Abstract translation: 根据本发明的一个方面，提供了一种构造插入件的方法。 在非导电层上形成导电层。 导电层具有通孔部分，非通孔部分以及第一和第二相对表面。 导电层的第一表面与非导电层相邻。 去除非导电层的部分以暴露导电层的第一表面的部分。 导电垫形成在导电层的第一表面和第二表面的暴露部分上。 去除导电层的非通孔部分以形成多个电分离的导体。 每个导体包括至少两个导电焊盘和导电层的通孔部分。