公开(公告)号：US20110031628A1

公开(公告)日：2011-02-10

申请号：US12841495

申请日：2010-07-22

Applicant: Rie TAKADA

Inventor： Rie TAKADA

IPC: H01L23/52 ,  H01L21/50

CPC classification number: H05K1/189 ,  G11C5/04 ,  H01L23/5385 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/1005 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2924/3511 ,  H05K1/0293 ,  H05K1/0295 ,  H05K1/141 ,  H05K1/144 ,  H05K1/147 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/225 ,  H05K2201/043 ,  H05K2201/055 ,  H05K2201/09127 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572 ,  H05K2203/176

Abstract: A semiconductor device module includes a first substrate layer on which a first semiconductor device is surface-mounted, a second substrate layer that is a layer laminated on a side of the first substrate layer on which the first semiconductor device is not surface-mounted, a second semiconductor device being surface-mounted on a surface of the second substrate layer and not on a side of the first substrate layer, and a hollow section that is a space sandwiched between the first substrate layer and the second substrate layer and formed on back sides of areas on which the first semiconductor device and the second semiconductor device are surface-mounted.

Abstract translation: 半导体器件模块包括第一衬底层，其上表面安装有第一半导体器件，第二衬底层，层叠在第一衬底层的不具有第一半导体器件的表面安装的一侧上的层， 第二半导体器件被表面安装在第二衬底层的表面上而不是在第一衬底层的一侧上，中空部分是夹在第一衬底层和第二衬底层之间并形成在第二衬底层的背面上的空间 的第一半导体器件和第二半导体器件表面安装的区域。

公开(公告)号：US20100025087A1

公开(公告)日：2010-02-04

申请号：US12489864

申请日：2009-06-23

Applicant: Michimasa TAKAHASHI

Inventor： Michimasa TAKAHASHI

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K3/4697 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/183 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/308 ,  Y10T29/49124 ,  Y10T29/49158 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flex-rigid wiring board including a rigid substrate including a rigid base material and a conductor layer, and a flexible substrate having a conductor layer. The conductor layer of the flexible substrate is electrically connected to the conductor layer of the rigid substrate. The rigid substrate has a recessed portion which is formed on a surface of the rigid substrate and which accommodates an electronic component.

Abstract translation: 一种柔性刚性布线板，包括刚性基板，其包括刚性基材和导体层，以及柔性基板，具有导体层。 柔性基板的导体层电连接到刚性基板的导体层。 刚性基板具有形成在刚性基板的表面上并且容纳电子部件的凹部。

公开(公告)号：US07596863B2

公开(公告)日：2009-10-06

申请号：US11652633

申请日：2007-01-12

Applicant: Ashwinkumar C. Bhatt ,  Robert J. Harendza ,  Robert M. Japp

Inventor： Ashwinkumar C. Bhatt ,  Robert J. Harendza ,  Robert M. Japp

IPC: H05K3/36

CPC classification number: H05K1/117 ,  H05K1/112 ,  H05K3/4611 ,  H05K2201/09127 ,  H05K2201/0919 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2203/061 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.

Abstract translation: 制造印刷电路板的方法，其中至少三个基板被对准并结合在一起（例如，使用层压）。 两个基板具有形成在其中的开口，每个开口包括位于其中的盖构件。 在层压期间，用于密封和防止介电材料（例如树脂）的盖构件在层压期间液化以接触内（第一）衬底的相对表面上的导电层。 因此，PCB在其中形成有突出边缘部分或多个空腔，使得可以使用边缘连接器等对PCB进行电连接。

公开(公告)号：US20090026604A1

公开(公告)日：2009-01-29

申请号：US12216375

申请日：2008-07-02

Applicant: Joon-Sik Shin ,  Nobuyuki Ikeguchi ,  Keungjin Sohn ,  Joung-Gul Ryu ,  Sang-Youp Lee ,  Jung-Hwan Park ,  Ho-Sik Park

Inventor： Joon-Sik Shin ,  Nobuyuki Ikeguchi ,  Keungjin Sohn ,  Joung-Gul Ryu ,  Sang-Youp Lee ,  Jung-Hwan Park ,  Ho-Sik Park

IPC: H01L21/58 ,  H01L23/14

CPC classification number: H01L23/145 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/068 ,  H05K2201/09127 ,  H05K2201/09536 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: A semiconductor plastic package and a method of fabricating the semiconductor plastic package are disclosed. A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.

Abstract translation: 公开了一种半导体塑料封装及其制造方法。 制造半导体塑料封装的方法可以包括：提供包括至少一个焊盘并且具有9ppm /℃或更低的热膨胀系数的芯板; 在芯板上堆叠堆积绝缘层; 通过去除所述积层绝缘层的一部分使得所述垫暴露于外部而形成开口; 并将半导体芯片放置在开口中并将半导体芯片与焊盘电连接。 该方法可以用于在半导体芯片和电路板之间的连接中提供更高的可靠性。

公开(公告)号：US20080286696A1

公开(公告)日：2008-11-20

申请号：US11987347

申请日：2007-11-29

Applicant: Yukihiro Ueno ,  Masatoshi Mori

Inventor： Yukihiro Ueno ,  Masatoshi Mori

IPC: G03F7/20

CPC classification number: H05K3/4691 ,  H05K3/281 ,  H05K3/386 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/09127 ,  H05K2201/09781 ,  H05K2203/0228

Abstract: In one embodiment, the invention has a step of forming an inner layer circuit pattern portion and a lead pattern portion, a step of forming a dummy pattern that indicates the range of the lead pattern portion on the outer layer base material, a step of forming an interlayer adhesive layer on a surface of the outer layer base material where the dummy pattern has been formed, a step of applying, corresponding to the dummy pattern, a resin film to the interlayer adhesive layer, a step of layering the outer layer base material on the inner layer base material via the interlayer adhesive layer with the position of the resin film matched to the position of the lead pattern portion, a step of forming the outer layer circuit pattern portion corresponding to the inner layer circuit pattern portion, and a step of removing the interlayer adhesive layer and the outer layer base material layered on the resin film.

Abstract translation: 在一个实施例中，本发明具有形成内层电路图形部分和引线图案部分的步骤，形成表示外层基材上的引线图案部分的范围的虚设图形的步骤，形成步骤 在形成有虚设图案的外层基材的表面上的层间粘合剂层，将对应于虚设图案的树脂膜涂布到层间粘合剂层的步骤，将外层基材 在树脂膜的位置与引线图案部的位置一致的情况下，通过层间粘合剂层在内层基材上形成与内层电路图案部对应的外层电路图形部的工序， 去除层叠粘合剂层和层叠在树脂膜上的外层基材。

公开(公告)号：US07443016B2

公开(公告)日：2008-10-28

申请号：US11163309

申请日：2005-10-13

Applicant: Yun-Lung Tsai ,  Yu-Chieh Tsai ,  Chien-Chih Chen ,  Chien-Ping Huang

Inventor： Yun-Lung Tsai ,  Yu-Chieh Tsai ,  Chien-Chih Chen ,  Chien-Ping Huang

IPC: H01L23/06 ,  H01L23/12 ,  H01L23/04 ,  H01L23/28

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/15162 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K3/284 ,  H05K2201/09127 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract translation: 提供半导体器件及其制造方法。 具有至少一个倾斜侧的开口形成在基板上。 至少一个芯片和至少一个无源部件安装在基板上。 在基板上形成具有切口角的密封剂，以封装芯片和无源部件，其中密封剂的切口角与开口的倾斜侧隔开预定距离。 进行切割处理以切割密封剂以形成具有倒角的包装。 封装被嵌入盖子中以形成半导体器件，其中位于开口的倾斜侧和密封剂的切除角之间的基底的一部分从密封剂暴露出来以形成暴露部分。 本发明还提供了一种用于半导体器件的载体。

公开(公告)号：US20080128384A1

公开(公告)日：2008-06-05

申请号：US11874286

申请日：2007-10-18

Applicant: Hiroyuki FUJITA ,  Yasutaka OCHIAI ,  Minoru KUBOTA

Inventor： Hiroyuki FUJITA ,  Yasutaka OCHIAI ,  Minoru KUBOTA

IPC: H01B13/00

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/386 ,  H05K2201/09127 ,  H05K2201/0919 ,  H05K2203/063

Abstract: An adhesive layer, an insulating layer and a copper foil are laminated together on both surfaces of a metallic base material by way of for example thermal press molding. In this case, openings (window holes) are formed in opposed positions on a portion of the adhesive layer. A circuit pattern is formed by etching on the copper foil in this state, followed by an external shape machining step of executing separation treatment reaching the metallic base material in predetermined positions including the openings. After that, a part of the insulating layer is cut off along the edge of the opening to obtain a circuit board with the end of the metallic base material exposed.

Abstract translation: 粘合剂层，绝缘层和铜箔通过例如热压成型层叠在金属基材的两面上。 在这种情况下，在粘合剂层的一部分的相对位置上形成开口（窗孔）。 在该状态下通过对铜箔进行蚀刻而形成电路图案，接着进行外部形状加工步骤，在包括开口的预定位置执行到达金属基材的分离处理。 之后，绝缘层的一部分沿着开口的边缘被切断，以获得露出金属基材端部的电路板。

公开(公告)号：US20080106288A1

公开(公告)日：2008-05-08

申请号：US11973793

申请日：2007-10-09

Applicant: Michael Rosenblatt ,  W. Bryson Gardner ,  Amir Salehi ,  Tony Aghazarian

Inventor： Michael Rosenblatt ,  W. Bryson Gardner ,  Amir Salehi ,  Tony Aghazarian

IPC: G01R31/02

CPC classification number: G01R1/0408 ,  G01R31/2818 ,  H05K1/0268 ,  H05K3/0052 ,  H05K3/403 ,  H05K2201/09127 ,  H05K2201/09181

Abstract: Circuit boards are provided that include a functional portion and at least one removable test point portion. The removable test point portion may include test points which are accessed to verify whether the functional portion is operating properly or whether installed electronic components are electrically coupled to the board. If multiple boards are manufactured together on a single panel (in which the individual boards are broken off), the test points can be placed on bridges (e.g., removable portions) that connect the individual boards together during manufacturing and testing. Configurable test boards are also provided that can be adjusted to accommodate circuit boards of different size and electrical testing requirements. Methods and systems for testing these circuit boards are also provided.

Abstract translation: 提供了包括功能部分和至少一个可拆卸测试点部分的电路板。 可拆卸测试点部分可以包括被访问以验证功能部分是否正常操作或者是否安装的电子部件电耦合到板的测试点。 如果在单个面板（其中单独的电路板被断开）中一起制造多个电路板，则测试点可以放置在在制造和测试期间将各个电路板连接在一起的桥接器（例如，可拆卸部分）上。 还提供了可配置的测试板，可以调整以适应不同尺寸和电气测试要求的电路板。 还提供了用于测试这些电路板的方法和系统。

公开(公告)号：US20080047135A1

公开(公告)日：2008-02-28

申请号：US11895922

申请日：2007-08-28

Applicant: Shawn Arnold

Inventor： Shawn Arnold

IPC: H05K3/00

CPC classification number: H05K3/4691 ,  H05K2201/09127 ,  H05K2201/09845 ,  Y10T29/49124

Abstract: A rigid flex circuit board and a method of fabricating a rigid flex circuit board. The method comprising forming a stack of at least two layers of at least one of a flexible material, prepreg material, insulative material, or conductive material over a flexible core to form a structure, wherein the structure comprises a first rigid portion, a second rigid portion, a flexible portion extending between the first and second rigid portions, and a removable rigid portion extending between the first rigid portion and the second rigid portion, processing the structure to form interconnects; and removing the removable rigid portion.

Abstract translation: 刚性柔性电路板和制造刚性柔性电路板的方法。 该方法包括在柔性芯上形成柔性材料，预浸材料，绝缘材料或导电材料中的至少一层至少两层的叠层以形成结构，其中该结构包括第一刚性部分，第二刚性部分 部分，在第一和第二刚性部分之间延伸的柔性部分和在第一刚性部分和第二刚性部分之间延伸的可移除的刚性部分，处理该结构以形成互连; 并移除可拆卸的刚性部分。

公开(公告)号：US07326857B2

公开(公告)日：2008-02-05

申请号：US10992399

申请日：2004-11-18

Applicant: Philip Raymond Germann ,  Mark James Jeanson

Inventor： Philip Raymond Germann ,  Mark James Jeanson

IPC: H05K1/03

CPC classification number: H05K1/117 ,  H05K3/0044 ,  H05K3/4611 ,  H05K2201/09127 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2203/0228 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49821 ,  Y10T29/5313

Abstract: A method and structure are provided for creating printed circuit boards with stepped thickness. A non-laminating breakaway material layer is selectively placed between layers of the printed circuit board. A perimeter portion of the printed circuit board near the breakaway material layer is scored. Then the breakaway material layer and adjacent layers between the perimeter of the printed circuit board are removed.

Abstract translation: 提供了一种制造具有阶梯厚度的印刷电路板的方法和结构。 非层压分离材料层选择性地放置在印刷电路板的层之间。 对分离材料层附近的印刷电路板的周边部分进行刻痕。 然后去除印刷电路板的周边之间的分离材料层和相邻的层。