公开(公告)号：US06759318B1

公开(公告)日：2004-07-06

申请号：US10414597

申请日：2003-04-15

Applicant: Chien-Wei Chang

Inventor： Chien-Wei Chang

IPC: H01L2144

CPC classification number: H05K3/243 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/3473 ,  H05K3/385 ,  H05K3/427 ,  H05K3/4652 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/0315 ,  H01L2924/00

Abstract: A method for a manufacturing process of micro bump pitch IC substrates uses a dielectric layer to replace the conventional solder resist, then uses CCD high precision alignment laser drill to open up the defined bump pad lands, and fills them with via plating filled metal accompanied by etching to enlarge the bump pads, and finally plates the bum pads with Sn/Pb. This can simultaneously solve the problems of insufficient strength of bump pads, limitation of printing technology and being unable to apply the solder in the conventional technologies. The method can provide a higher packaging density, higher yield rate, and provides a total solution to the next generation high density IC design.

Abstract translation: 微凸块间距IC基板的制造工序的方法使用电介质层来代替常规的阻焊剂，然后使用CCD高精度定位激光钻孔机来打开定义的凸块焊盘区域，并通过电镀填充金属填充它们，伴随着 蚀刻以扩大凸块，最后用Sn / Pb涂覆凸块。 这可以同时解决凸起焊盘强度不足，印刷技术的局限性和传统技术中不能应用焊料的问题。 该方法可以提供更高的封装密度，更高的产率，并为下一代高密度IC设计提供全面的解决方案。

公开(公告)号：US20040040645A1

公开(公告)日：2004-03-04

申请号：US10435183

申请日：2003-05-09

Applicant: 3M Innovative Properties Company

Inventor： Frank J. Bottari

IPC: B44C001/165 ,  B32B003/00 ,  B32B031/00 ,  B32B015/00

CPC classification number: G06F3/045 ,  H05K3/207 ,  H05K3/28 ,  H05K2201/0284 ,  H05K2201/09436 ,  H05K2203/0531 ,  Y10S428/914 ,  Y10T29/49117 ,  Y10T428/24777 ,  Y10T428/24917

Abstract: A method of applying an edge electrode pattern to a touch screen panel including printing an edge electrode pattern on decal paper; applying a cover coat over the electrode pattern; removing the decal paper; and transferring the edge electrode pattern to a touch screen panel. A decal to be used in accordance with this method.

Abstract translation: 一种将边缘电极图案应用于触摸屏面板的方法，包括在贴纸上印刷边缘电极图案; 在电极图案上涂覆覆盖层; 去除贴纸; 并将边缘电极图案转移到触摸屏面板。 按照这种方法使用的贴花。

公开(公告)号：US06693359B1

公开(公告)日：2004-02-17

申请号：US10351328

申请日：2003-01-27

Applicant: Yi-Ching Lin

Inventor： Yi-Ching Lin

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09436 ,  H05K2201/098 ,  Y02P70/611 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A semiconductor package, which is to attach an electric device, such as a die, thereon and electrically connect therewith, has a substrate with a conductor pattern thereon. The conductor pattern consists of a plurality of traces in a specific layout. The conductor pattern has conducting portions on which is provided with a conductor member respectively. The conductor members locate at positions above the conducting portion of the conductor pattern with a bottom surface thereof electrically connecting a top surface of the conducting portion. A solder mask is provided on the substrate sheltering the conductor pattern but exposing at least a top surface of the conductor member. Whereby, the conductor can electrically connect the electric device via the conductor members.

Abstract translation: 在其上附着诸如模具的电气装置并与其电连接的半导体封装件具有其上具有导体图案的基板。 导体图案由特定布局中的多个迹线组成。 导体图案具有分别设有导体部件的导电部分。 导体构件位于导体图案的导电部分上方的位置处，其底表面电连接导电部分的顶表面。 在衬底上设置阻焊导体图形，但暴露于导体构件的至少顶表面的焊接掩模。 由此，导体可以经由导体构件电连接电子装置。

公开(公告)号：US20030034565A1

公开(公告)日：2003-02-20

申请号：US10224285

申请日：2002-08-19

Inventor： James Jaen-Don Lan ,  Chien Wei Chang

IPC: H01L023/48

CPC classification number: H01L23/49894 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/09436 ,  H05K2201/10674 ,  H01L2924/00

Abstract: The present invention discloses a flip-chip package assembly. The flip-chip package assembly includes a flipped IC chip having a plurality of input/output terminals mounted onto a substrate wherein the substrate includes a plurality of conductive columns disposed on top the substrate with each of the conductive columns disposed at a location corresponding to a location of one of the input/output terminals on the IC chip. The substrate further includes a layer of low-modulus polymer layer disposed on top of the substrate surrounding and bonding to the conductive columns to flexibly yield to bending of the conductive columns.

Abstract translation: 本发明公开了一种倒装芯片封装组件。 倒装芯片封装组件包括具有安装在衬底上的多个输入/输出端子的翻转IC芯片，其中衬底包括设置在衬底上的多个导电柱，每个导电柱设置在对应于 IC芯片上的输入/输出端子之一的位置。 衬底进一步包括一层低模量聚合物层，该层设置在衬底的顶部，该层围绕并结合到导电柱上以灵活地屈服于导电柱的弯曲。

公开(公告)号：US20030020150A1

公开(公告)日：2003-01-30

申请号：US10251072

申请日：2002-09-19

Applicant: International Business Machines Corporation

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

IPC: H01L023/02

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

公开(公告)号：US06492600B1

公开(公告)日：2002-12-10

申请号：US09340758

申请日：1999-06-28

Applicant: Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

Inventor： Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

IPC: H05K109

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

Abstract translation: 一种用于形成其中形成有受体垫的芯片载体结构和方法。 该结构包括在表面上具有导电元件的电路化基板，安装在电路化基板上的外部电介质层，其中开口位于导电元件上方以形成微孔。 首先处理微孔的壁以增强铜的粘附性，然后电镀以提供受体垫。 最后，在微孔内沉积焊膏以产生焊料沉积物或凸块。

公开(公告)号：US06372622B1

公开(公告)日：2002-04-16

申请号：US09426982

申请日：1999-10-26

Applicant: Qing Tan ,  Stanley Craig Beddingfield ,  Douglas G. Mitchell

Inventor： Qing Tan ,  Stanley Craig Beddingfield ,  Douglas G. Mitchell

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/113 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/09436 ,  H05K2201/09563 ,  H05K2203/043 ,  H05K2203/054 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (10) having a bond pad (12), and forming a first masking layer (20) overlying the bond pad (12). The first masking layer (20) is patterned to form a first opening (22) overlying at least a portion of the bond pad (12). A second masking layer (40) is formed overlying the first masking layer (20), and the second masking layer (40) is patterned to form a second opening (42) overlying at least a portion of the first opening (22). The method further includes forming a stud (30) at least within the first opening (22) and a solder bump (60) at least within the second opening (42).

Abstract translation: 本发明的实施例大体上涉及焊料凸点形成和半导体器件组件。 与形成凸块结构的方法相关的一个实施例包括提供具有接合焊盘（12）的半导体器件（10），以及形成覆盖接合焊盘（12）的第一掩蔽层（20）。 图案化第一掩模层（20）以形成覆盖至少一部分接合焊盘（12）的第一开口（22）。 第二掩模层（40）形成在第一掩模层（20）上方，并且第二掩模层（40）被图案化以形成覆盖第一开口（22）的至少一部分的第二开口（42）。 该方法还包括至少在第一开口（22）内形成螺柱（30）和至少在第二开口（42）内的焊料凸块（60）。

公开(公告)号：US20010032698A1

公开(公告)日：2001-10-25

申请号：US09886452

申请日：2001-06-21

Applicant: MicroTouch Systems, Inc.

Inventor： Frank J. Bottari

IPC: B44C001/00

CPC classification number: G06F3/045 ,  H05K3/207 ,  H05K3/28 ,  H05K2201/0284 ,  H05K2201/09436 ,  H05K2203/0531 ,  Y10S428/914 ,  Y10T29/49117 ,  Y10T428/24777 ,  Y10T428/24917

Abstract: A method of applying an edge electrode pattern to a touch screen panel including printing an edge electrode pattern on decal paper; applying a cover coat over the electrode pattern; removing the decal paper; and transferring the edge electrode pattern to a touch screen panel. A decal to be used in accordance with this method.

Abstract translation: 一种将边缘电极图案应用于触摸屏面板的方法，包括在贴纸上印刷边缘电极图案; 在电极图案上涂覆覆盖层; 去除贴纸; 并将边缘电极图案转移到触摸屏面板。 按照这种方法使用的贴花。

公开(公告)号：US5461775A

公开(公告)日：1995-10-31

申请号：US230033

申请日：1994-04-19

Applicant: Kouji Tanabe ,  Naohiro Nishioka

Inventor： Kouji Tanabe ,  Naohiro Nishioka

IPC: H05K3/28 ,  H05K1/00 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/24 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K3/321 ,  H05K1/114 ,  H05K3/245 ,  H05K1/0393 ,  H05K1/095 ,  H05K1/181 ,  H05K2201/09436 ,  H05K2201/10106 ,  H05K2201/10651 ,  H05K2201/10977 ,  H05K2203/0285 ,  H05K2203/065 ,  H05K2203/1311 ,  H05K2203/1453 ,  H05K3/4069 ,  H05K3/4644 ,  H05K3/4664 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A flexible printed circuit board is constituted with a first insulation film covering a first insulating resist layer, a second insulation film covering a second insulating resist layer and a printed circuit formed between the first insulating resist layer and the second insulating resist layer, and a terminal of an electronic component is disposed on the printed circuit, and the second insulation film is pressed and heated.

Abstract translation: 柔性印刷电路板由覆盖第一绝缘抗蚀剂层的第一绝缘膜，覆盖第二绝缘抗蚀剂层的第二绝缘膜和形成在第一绝缘抗蚀剂层和第二绝缘抗蚀剂层之间的印刷电路构成，端子 的电子部件设置在印刷电路上，第二绝缘膜被按压和加热。

公开(公告)号：US4756929A

公开(公告)日：1988-07-12

申请号：US681686

申请日：1984-12-14

Applicant: Donald F. Sullivan

Inventor： Donald F. Sullivan

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/34 ,  H05K3/46 ,  B05D5/12 ,  G03C5/00 ,  H05K1/00 ,  H05K3/02

CPC classification number: H05K3/107 ,  H05K3/184 ,  H05K3/242 ,  H05K3/3452 ,  H05K1/117 ,  H05K2201/09036 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2201/09981 ,  H05K2203/025 ,  H05K2203/054 ,  H05K2203/056 ,  H05K2203/0571 ,  H05K2203/0577 ,  H05K2203/066 ,  H05K2203/0759 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/108 ,  H05K3/4661 ,  Y10T29/49155

Abstract: Densely packed high resolution printed wiring boards may be achieved by providing channels below grade in a substrate planar surface, thereby providing greater conductor width for closely spaced conductors. By mechanically removing the substrate surface between the channels, high virtual resolution is obtained with high quality conductors and insulation spacings of the order of about 0.003 inch, and with actual conductor widths of greater than 0.012 inch. Thus the packing density of printed wiring patterns may be increased significantly. Also the quality of conductor adherence and conductivity is improved. Thus a non-critical and inexpensive process unexpectedly provides an improved quality, more precise printed wiring pattern.

Abstract translation: 密集的高分辨率印刷线路板可以通过在基板平面中提供低于等级的通道，从而为紧密间隔的导体提供更大的导体宽度。 通过机械地去除通道之间的基板表面，可以获得具有约0.003英寸量级的高质量导体和绝缘间距以及大于0.012英寸的实际导体宽度的高虚拟分辨率。 因此，可以显着地增加印刷布线图案的包装密度。 导体粘附性和导电性也提高了。 因此，非关键和廉价的工艺意外地提供了改进的质量，更精确的印刷布线图案。