公开(公告)号：US06585903B1

公开(公告)日：2003-07-01

申请号：US09655985

申请日：2000-09-06

Applicant: Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

Inventor： Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

IPC: C23F100

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2201/09745 ,  H05K2201/0979 ,  H05K2201/09854 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics by causing a first insulating layer to separate from a portion of a first conductive layer of the multi-layer electronic circuit board 10 which allows for communication by and between some or all of the various component containing surfaces, and portions of the formed multi-layer electrical circuit board 10, which selectively allows components contained within and/or upon these portions and surfaces to be interconnected.

Abstract translation: 多层电子电路板设计10具有选择性地形成的孔或空腔26，其通过使第一绝缘层与多层电子电路板10的第一导电层的一部分分离而具有改善的焊料润湿特性，其允许 用于与部分或全部各种部件容纳表面之间进行通信，以及形成的多层电路板10的部分，其选择性地允许包含在这些部分和表面内部和/或之上的部件互连。

公开(公告)号：US06499214B2

公开(公告)日：2002-12-31

申请号：US09812449

申请日：2001-03-20

Applicant: Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

Inventor： Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

IPC: H05K320

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US06495053B1

公开(公告)日：2002-12-17

申请号：US09651765

申请日：2000-08-30

Applicant: Lawrence Leroy Kneisel ,  Mohan R. Paruchuri ,  Vivek Amir Jalrazbhoy ,  Vladimir Stoica

Inventor： Lawrence Leroy Kneisel ,  Mohan R. Paruchuri ,  Vivek Amir Jalrazbhoy ,  Vladimir Stoica

IPC: H01B124

CPC classification number: H05K3/4641 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2203/1438

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.

Abstract translation: 具有选择性地形成的孔或空腔26的多层电子电路板设计10，并且其包括槽或槽20,22，其有效地选择性地捕获液化的粘合剂材料，从而基本上防止粘合剂材料进入孔26。

公开(公告)号：US06492201B1

公开(公告)日：2002-12-10

申请号：US09119079

申请日：1998-07-10

Applicant: Belgacem Haba

Inventor： Belgacem Haba

IPC: H01L2148

CPC classification number: H01L24/50 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/386 ,  H05K3/423 ,  H05K3/445 ,  H05K2201/0382 ,  H05K2201/09554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electrically conductive article such as a sheet having holes therein is coated with a dielectric polymer using a multi-stage electrophoretic deposition process. A coating of uncured polymer is deposited electrophoretically and then cured. After the first polymer is cured, the part is subject to a further electrophoretic deposition process and further curing. Use of a second electrophoretic deposition step allows effective coating of parts having small holes without plugging the holes. The coated parts may be used as microelectronic connection components such as chip carriers used in packaging semiconductor chips.

Abstract translation: 使用多阶段电泳沉积工艺，用介电聚合物涂覆诸如其中具有孔的片的导电制品。 将未固化的聚合物涂层电泳沉积，然后固化。 在第一聚合物固化后，该部分进行进一步的电泳沉积工艺并进一步固化。 使用第二电泳沉积步骤允许有效涂覆具有小孔的部件而不堵塞孔。 涂覆部件可以用作微电子连接部件，例如用于封装半导体芯片的芯片载体。

公开(公告)号：US20020166840A1

公开(公告)日：2002-11-14

申请号：US10184968

申请日：2002-07-01

Applicant: TOYO KOHAN CO., LTD.

Inventor： Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida

IPC: B32B003/00

CPC classification number: H05K3/062 ,  H05K3/20 ,  H05K3/44 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10S428/901 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/24917

Abstract: In the present invention, which produces a clad sheet for a multilayered printed circuit board capable of being economically manufactured and having excellent performance, a multilayered printed circuit board using thereof and a manufacturing method thereof, a multilayered printed circuit board is manufactured by forming clad sheet for a multilayered printed circuit board 34 by laminating copper foil 19, 24, 33 which are to be formed into conductor layer 10, 17, 18 and nickel plating 20, 21 which are to be etching-stopper layer and simultaneously press-bonding both, producing a base by selectively etching clad sheet for a multilayered printed circuit board 34, forming outer conductor layer 15, 16 on the surface of the base and simultaneously making patterning, and electrically connecting among conductor layer 10, 15, 16 by interposing columnar conductor 17, 18 formed by etching copper foil 19, 24, 33 and nickel plating 20, 21.

Abstract translation: 在本发明中，其制造能够经济地制造并具有优异性能的多层印刷电路板用复合板，使用其的多层印刷电路板及其制造方法，多层印刷电路板通过形成包覆层 对于多层印刷电路板34，通过将要形成导体层10,17,18和作为蚀刻停止层并同时压接两者的镍镀层20,21的铜箔19,24,33层压， 通过选择性地蚀刻用于多层印刷电路板34的包覆片来形成基底，在基底的表面上形成外部导体层15,16并同时进行构图，并且通过插入柱状导体17将导体层10,15,16电连接 18，通过蚀刻铜箔19,24,33和镀镍20,21形成。

公开(公告)号：US06467161B2

公开(公告)日：2002-10-22

申请号：US09812989

申请日：2001-03-20

Applicant: Achyuta Achari ,  Brenda Joyce Nation ,  Delin Li ,  Lakhi N. Goenka ,  Richard Keith McMillan ,  Vivek A. Jairazbhoy

Inventor： Achyuta Achari ,  Brenda Joyce Nation ,  Delin Li ,  Lakhi N. Goenka ,  Richard Keith McMillan ,  Vivek A. Jairazbhoy

IPC: H05K320

CPC classification number: H05K3/4685 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method 10, 110 for making multi-layer electronic circuit boards 82, 148 having metallized apertures 18, 20, 118, 120 which may be selectively and electrically connected to a source of ground potential.

Abstract translation: 一种用于制造具有金属化孔18,20,118,120的多层电子电路板82,148的方法10,110，其可以选择性地和电连接到地电位源。

公开(公告)号：US20020085364A1

公开(公告)日：2002-07-04

申请号：US10067551

申请日：2002-02-05

Inventor： Francis J. Downes JR. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC: H05K009/00

CPC classification number: H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

Abstract translation: 提供电子封装，以及制造电子封装的方法。 封装包括半导体芯片和具有诸如烯丙基化表面层的高密度互连层的多层互连结构。 半导体芯片包括通过多个焊接连接而连接到多层互连结构的其一个表面上的多个接触构件。 多层互连结构适于将半导体芯片与另外多个焊料连接的电路化基板（例如，电路板）电互连，并且包括由具有选定厚度和热系数的材料组成的导热层 从而基本上防止所述第一多个导电构件和半导体芯片之间的焊料连接的故障。 电子封装还包括具有有效模数的电介质材料，以确保在操作期间多层互连结构的充分符合性。 烯丙基化表面层具有能够承受电子封装的热循环操作期间产生的热应力的性质。

公开(公告)号：US20010037898A1

公开(公告)日：2001-11-08

申请号：US09815234

申请日：2001-03-22

Inventor： Bharat Z. Patel ,  Jay D. Baker ,  Mohan R. Paruchuri

IPC: H05K001/11

CPC classification number: H05K3/462 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method 10, 90 for making a multi-layer electronic circuit board 82, 168 including the steps of forming at least one protuberance 15, 100 upon an electrically conductive member 12, 92 and adding additional electrically conductive layers of material 34, 56, 58, 104, 114, 138, 140 to the member 12, 92 while selectively extending the protuberance 15, 100 within the layers 82, 168, thereby forming a circuit board 82, 168. A portion of the formed circuit board may be etched in order to selectively create air-bridges 86 or interconnection portions 164.

Abstract translation: 一种用于制造多层电子电路板82,168的方法10,90，包括在导电构件12,92上形成至少一个突起15,100的步骤，并且添加另外的材料34,56,58的导电层 ，104,114,138,140连接到构件12,92，同时在层82,168内选择性地延伸突起15,100，从而形成电路板82,168。形成的电路板的一部分可以按顺序蚀刻 以选择性地产生空气桥86或互连部分164。

公开(公告)号：US06247228B1

公开(公告)日：2001-06-19

申请号：US08989305

申请日：1997-12-12

Applicant: Thomas H. Distefano ,  Joseph Fjelstad

Inventor： Thomas H. Distefano ,  Joseph Fjelstad

IPC: H05K336

CPC classification number: H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2414 ,  H01R43/0256 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/326 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1744 ,  H01L2924/00

Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.

公开(公告)号：US06225572B1

公开(公告)日：2001-05-01

申请号：US09403966

申请日：1999-11-01

Applicant: Jean Marc Nicolaï ,  Marc Duarte

Inventor： Jean Marc Nicolaï ,  Marc Duarte

IPC: H05K116

CPC classification number: H05K3/3447 ,  H01R9/16 ,  H01R12/58 ,  H05K3/0061 ,  H05K3/44 ,  H05K2201/0382 ,  H05K2201/09554 ,  H05K2201/09745 ,  H05K2201/10401

Abstract: An assembly including a printed-circuit electronics card mounted on a metal substrate, and in electronic communication with the same, includes a capsule which is crimped into a cavity in the metal substrate and which extends through a hole in the electronics card, the edges of said hole being metallised, the capsule being soldered to the metallised area of the edges.

Abstract translation: 包括安装在金属基板上并与其电子连通的印刷电路电子卡的组件包括：胶囊，其被压接在金属基板中的空腔中并延伸穿过电子卡的孔， 所述孔被金属化，所述胶囊被焊接到边缘的金属化区域。