中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

549 records (took 0.022 seconds)

    Memory module
    53.
    发明申请
    Memory module 有权
    内存模块

    公开(公告)号：US20080123303A1

    公开(公告)日：2008-05-29

    申请号：US11987080

    申请日：2007-11-27

    Applicant: Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    Inventor： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    IPC: H05K7/00

    CPC classification number: H05K1/181 ,  G11C5/00 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611

    Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

    Abstract translation: 存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器 在与存储芯片MC3相对的位置经由模块基板。 连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置 的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。因此，可以使布线部分的布线长度足够短。

    MULTI-LAYER PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF
    55.
    发明申请
    MULTI-LAYER PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF 有权
    多层印刷接线板及其制造方法

    公开(公告)号：US20080060840A1

    公开(公告)日：2008-03-13

    申请号：US11832892

    申请日：2007-08-02

    Applicant: Youhong WU

    Inventor： Youhong WU

    IPC: H01R12/06 ,  H05K3/46

    CPC classification number: H05K1/115 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49165

    Abstract: A multi-layer printed wiring board has a core substrate, a throughhole structure, a first interlayer insulation layer, a first via, a second interlayer insulation layer and a second via. The core substrate has a throughhole opening, and the throughhole structure is formed in the throughhole opening. The first interlayer insulation layer is formed over the core substrate. The first via is formed in the first interlayer insulation layer and has a bottom portion having a first radius. The second interlayer insulation layer is formed over the first interlayer insulation layer and the first via. The second via is formed in the second interlayer insulation layer and has a bottom portion having a second radius greater than the first radius. The first via is positioned inside a circle having a radius (D1) from a gravity center of the throughhole opening, and the radius (D1) of the circle satisfies a formula, (D1)=(R)+(r)/3, where (R) represents a radius of the throughhole opening and (r) represents the first radius of the first via.

    Abstract translation: 多层印刷电路板具有核心基板，通孔结构，第一层间绝缘层，第一通孔，第二层间绝缘层和第二通孔。 核心基板具有通孔开口，并且通孔结构形成在通孔开口中。 在芯基板上形成第一层间绝缘层。 第一通孔形成在第一层间绝缘层中，并且具有第一半径的底部。 第二层间绝缘层形成在第一层间绝缘层和第一通孔之上。 第二通孔形成在第二层间绝缘层中，并且具有大于第一半径的第二半径的底部。 第一通孔位于从通孔开口重心的半径（D1）的圆内，圆的半径（D1）满足式（D1）=（R）+（r）/ 3， 其中（R）表示通孔开口的半径，（r）表示第一通孔的第一半径。

    Printed circuit board for high speed, high density electrical connector with improved cross-talk minimization, attenuation and impedance mismatch characteristics
    56.
    发明申请
    Printed circuit board for high speed, high density electrical connector with improved cross-talk minimization, attenuation and impedance mismatch characteristics 失效
    印刷电路板用于高速，高密度电连接器，具有改进的串扰最小化，衰减和阻抗失配特性

    公开(公告)号：US20080030970A1

    公开(公告)日：2008-02-07

    申请号：US11808642

    申请日：2007-06-12

    Applicant: Jason Payne ,  Mark Gailus ,  Leon Khilchenko ,  Huilin Ren

    Inventor： Jason Payne ,  Mark Gailus ,  Leon Khilchenko ,  Huilin Ren

    IPC: H05K1/11

    CPC classification number: H01R13/6477 ,  H01R12/714 ,  H01R13/514 ,  H01R13/6471 ,  H01R13/6587 ,  H05K1/0219 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2201/10189

    Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias. For each of the plurality of rows of the conductive vias, there are at least twice as many ground conductor connecting conductive vias as signal conductor connecting conductive vias and the conductive vias are positioned relative to one another so that for each signal conductor connecting conductive via, there are ground conductor connecting conductive vias adjacent either side of the signal conductor connecting conductive via.

    Abstract translation: 在优选实施例中，公开了一种印刷电路板，其具有提供配合接口的表面，电连接器具有信号导体和接地导体。 印刷电路板包括多个堆叠的电介质层，其中导体设置在多个电介质层中的至少一个上。 配合接口包括以多行排列的多个导电通孔，多个导电通孔延伸穿过多个电介质层的至少一部分，多个导电通孔中的至少一个与导体相交。 多个导电通孔包括连接导电通孔的信号导体和连接导电通孔的接地导体。 对于导电通孔的多行中的每一行，存在至少两倍的接地导体，其连接导电通孔，作为连接导电通孔的信号导体，并且导电通孔相对于彼此定位，使得对于连接导电通孔的每个信号导体， 有接地导体连接导电通孔，邻近信号导体的任一侧连接导电通孔。

    Routing power and ground vias in a substrate
    57.
    发明授权
    Routing power and ground vias in a substrate 失效
    在基板中布线电源和接地通孔

    公开(公告)号：US07327583B2

    公开(公告)日：2008-02-05

    申请号：US10939654

    申请日：2004-09-13

    Applicant: Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Karl Bois

    Inventor： Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Karl Bois

    IPC: H01R12/16 ,  H05K1/11

    CPC classification number: H01L23/50 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0263 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/115 ,  H05K2201/09627 ,  H01L2924/00

    Abstract: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.

    Abstract translation: 公开了一种用于在多层衬底中布线过孔的方法。 方法的一个实施例可以包括提供具有内部结合表面的多层基底，所述内部结合表面具有多个内部接合垫和具有多个外部键合垫的外部结合表面。 基于通孔图案，多个电源通孔和接地通孔可以从内部接合表面和外部接合表面之间的第一再分配层路由到第一再分配层和外部接合表面之间的第二再分配层。 通孔图案可以包括以基本上等于与多层基板相关联的最小路由间距的间隔相互隔开相邻的方式布置电力通孔和接地。

    Routing vias in a substrate from bypass capacitor pads
    58.
    发明授权
    Routing vias in a substrate from bypass capacitor pads 失效
    从旁路电容器衬垫的衬底中路由通孔

    公开(公告)号：US07326860B2

    公开(公告)日：2008-02-05

    申请号：US11446669

    申请日：2006-06-05

    Applicant: Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

    Inventor： Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

    IPC: H01R12/04 ,  H05K1/11

    CPC classification number: H01L23/5384 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/0979 ,  H01L2924/00

    Abstract: A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.

    Abstract translation: 公开了具有接合面的多层基板。 衬底的一个实施例可以包括设置在接合表面上的旁路电容器连接焊盘。 旁路电容连接焊盘可能具有旁路电容器功率垫和旁路电容接地垫。 衬底还可以包括从旁路电容器功率焊盘路由到与接合表面间隔开的第一再分配层的多个电源通孔和从旁路电容器接地焊盘路由到第一再分配层的多个接地通孔。 衬底还可以包括根据功率和接地经由图案阵列从第一再分配层路由到第二再分布层的多个电源和接地通孔，其中多个接地通孔在第一再分配层处被点动到多个 电源通孔通过图案阵列形成电源和接地。

    High-speed signal transmission structure having parallel disposed and serially connected vias
    59.
    发明申请
    High-speed signal transmission structure having parallel disposed and serially connected vias 有权
    高速信号传输结构具有平行布置和串联连接的通孔

    公开(公告)号：US20080017411A1

    公开(公告)日：2008-01-24

    申请号：US11492514

    申请日：2006-07-24

    Applicant: Yen-Hao Chen

    Inventor： Yen-Hao Chen

    IPC: H05K1/11 ,  H01R12/04

    CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09627

    Abstract: A high-speed signal transmission structure having parallel disposed and serially connected vias is disclosed. The structure is applicable to a multi-layered circuit board such as a high-speed digital circuit board for forming a high-speed signal transmission circuit on the high-speed digital circuit board. The structure includes a pair of parallel disposed and serially connected vias for connecting an upper conductive circuit installed on an upper layer of the multi-layered circuit board and a lower conductive circuit installed on a lower layer of the multi-layered circuit board. Compared with the prior art, an open stub formed by the remaining portion of the vias has become shorter, thereby reducing a resonance effect affecting the quality of signal transmission.

    Abstract translation: 公开了一种具有平行布置且串联连接的通孔的高速信号传输结构。 该结构适用于高速数字电路板上形成高速信号传输电路的高速数字电路板等多层电路板。 该结构包括一对平行布置和串联连接的通孔，用于连接安装在多层电路板的上层上的上导电电路和安装在多层电路板的下层上的下导电电路。 与现有技术相比，由通孔的剩余部分形成的开路短路已经变短，从而降低了影响信号传输质量的共振效应。

    Testing a high speed serial bus within a printed circuit board
    60.
    发明申请
    Testing a high speed serial bus within a printed circuit board 失效
    测试印刷电路板内的高速串行总线

    公开(公告)号：US20080003884A1

    公开(公告)日：2008-01-03

    申请号：US11480087

    申请日：2006-06-30

    Applicant: David Louis Spengler ,  Bill Pagano

    Inventor： David Louis Spengler ,  Bill Pagano

    IPC: H01R13/66

    CPC classification number: H05K1/0268 ,  H05K3/306 ,  H05K3/42 ,  H05K2201/09627 ,  H05K2201/1059 ,  H05K2203/175

    Abstract: An apparatus and associated method for analyzing a communications link between two components on a common PCB. The communications link has a pair of through-board conductors connected by a first conductive etching on one side of the PCB. The communications link further has second etchings on an opposite side of the PCB respectively connecting each of the through-board conductors to one of the components.

    Abstract translation: 一种用于分析公共PCB上的两个组件之间的通信链路的装置和相关联的方法。 通信链路具有通过PCB的一侧上的第一导电蚀刻而连接的一对贯通板导体。 通信链路还在PCB的相对侧上具有第二蚀刻，其分别将每个贯通板导体连接到其中一个部件。

Patent Agency Ranking