公开(公告)号：US20080116555A1

公开(公告)日：2008-05-22

申请号：US11649306

申请日：2007-01-04

Applicant: En-Min Jow

Inventor： En-Min Jow

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/71

CPC classification number: H01L23/3121 ,  H01L23/49805 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10727 ,  Y02P70/611 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure of a memory card includes a Printed Circuit Board (PCB) and at least one chip package. Plural solder pads are set on the upper surface of the PCB, and an exposed golden finger is set on the bottom surface of the PCB. Every chip package includes at least one chip and a substrate. At least one layer of trace is set inside the substrate, and the trace has plural conductive terminals exposed on the bottom surface of the substrate. The conductive terminals are adhered to and electrically connected with the solder pads. A package method for a memory card includes: providing at least one chip package using a substrate as a chip carrier; adhering the chip package onto a PCB to electrically connect the chip package and the PCB; and covering the chip package and the PCB.

Abstract translation: 存储卡的封装结构包括印刷电路板（PCB）和至少一个芯片封装。 多个焊盘设置在PCB的上表面，并且暴露的金手指放置在PCB的底表面上。 每个芯片封装包括至少一个芯片和基板。 在衬底内设置至少一层迹线，并且迹线具有暴露在衬底底表面上的多个导电端子。 导电端子被粘附并与焊盘电连接。 用于存储卡的封装方法包括：使用衬底作为芯片载体提供至少一个芯片封装; 将芯片封装粘贴到PCB上以电连接芯片封装和PCB; 并覆盖芯片封装和PCB。

公开(公告)号：US07372149B2

公开(公告)日：2008-05-13

申请号：US11115213

申请日：2005-04-27

Applicant: Makoto Yamamoto ,  Eiji Suematsu

Inventor： Makoto Yamamoto ,  Eiji Suematsu

IPC: H01L23/34

CPC classification number: H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01Q21/065 ,  H01Q23/00 ,  H05K1/0206 ,  H05K1/0243 ,  H05K1/113 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/09072 ,  H05K2201/0979 ,  H05K2201/10727 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A high frequency semiconductor apparatus is provided which prevents characteristics of a high frequency semiconductor element from being deteriorated so that the high frequency semiconductor element can be made to operate stably. The high frequency semiconductor apparatus is so configured that heat generated by a high frequency semiconductor element is sequentially conducted through a grounding via hole to a first ground layer, a first via hole, a first ground sublayer, a bonding material layer, a second ground layer, a second via hole, and a third ground layer.

Abstract translation: 提供一种高频半导体装置，其防止高频半导体元件的特性劣化，使得可以使高频半导体元件稳定地工作。 高频半导体装置的结构是使高频半导体元件产生的热量依次通过接地通孔传导到第一接地层，第一通孔，第一接地子层，接合材料层，第二接地层 ，第二通孔和第三接地层。

公开(公告)号：US07357288B2

公开(公告)日：2008-04-15

申请号：US10891524

申请日：2004-07-15

Applicant: Naoto Hosotani ,  Kazuki Fukada ,  Keiichi Iwata ,  Daido Komyoji

Inventor： Naoto Hosotani ,  Kazuki Fukada ,  Keiichi Iwata ,  Daido Komyoji

IPC: B23K1/00

CPC classification number: B23K3/087 ,  B23K2101/40 ,  H01L24/75 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12042 ,  H05K3/3494 ,  H05K2201/10727 ,  H05K2203/0195 ,  H05K2203/1121 ,  H05K2203/1581 ,  H05K2203/304 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53178 ,  Y10T29/53191 ,  Y10T29/53261 ,  H01L2924/00014 ,  H01L2924/00

Abstract: When a component, that has a connection portion to be connected to an electrode of a board and a weak heat-resistant portion of a lower heat-resisting property than a fusing point of a connection material for connecting the electrode of the board with the connection portion, is connected to the board with interposition of connection material between the electrode of the board and the connection portion, a cooling member is brought into contact with the weak heat-resistant portion or its neighborhood while heating the connection material by heating the board brought in contact with a placement member, and a quantity of heat conducted to the weak heat-resistant portion via the board is reduced by being conducted to the cooling member, thereby performing fusing of the connection material while preventing occurrence of thermal damage to the weak heat-resistant portion.

Abstract translation: 当具有要连接到板的电极的连接部分和具有比用于将板的电极与连接件连接的连接材料的熔点低的耐热性能的弱耐热部分的部件 通过在板的电极和连接部之间插入连接材料而连接到板，冷却部件与弱耐热部或其附近接触，同时通过加热连接材料来加热板 与放置构件接触，并且通过被传导到冷却构件而减少通过板传导到弱耐热部分的热量，从而进行连接材料的熔合，同时防止对弱热的热损伤的发生 抵抗部分。

公开(公告)号：US20070235844A1

公开(公告)日：2007-10-11

申请号：US11697196

申请日：2007-04-05

Applicant: Hiroki Suzuki

Inventor： Hiroki Suzuki

IPC: H01L23/495

CPC classification number: H05K3/321 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/141 ,  H01L2224/1411 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H05K3/305 ,  H05K3/3442 ,  H05K2201/10674 ,  H05K2201/10727 ,  H05K2201/10977 ,  H05K2203/0425 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A mounting structure of an electronic device capable of properly enhancing a bonding strength between an insulating substrate and the electronic device is provided. An electrode and an earth electrode having a surrounding shape are formed on an insulating substrate. In addition, a non-metal area exposing a surface of the insulating substrate is provided in the surrounding shape. An earth terminal is provided on a position opposed to the non-metal area on a back surface of an electronic device. The non-metal area and the earth terminal are bonded to each other by a solder adhesive including solder particles and a resin as major components. The solder particles are agglomerated on the earth terminal, then a solder layer is formed, and the earth terminal and the non-metal area are bonded to each other by the resin layer. Accordingly, a bonding strength between the electronic device and the insulating substrate are properly enhanced.

Abstract translation: 提供能够适当地提高绝缘基板和电子装置之间的接合强度的电子装置的安装结构。 在绝缘基板上形成具有周围形状的电极和接地电极。 此外，露出绝缘基板的表面的非金属区域设置在周围的形状。 接地端子设置在与电子设备的背面上的非金属区域相对的位置。 非金属区域和接地端子通过包括焊料颗粒和树脂作为主要成分的焊料粘合剂相互结合。 焊料颗粒在接地端子上聚集，然后形成焊料层，并且接地端子和非金属区域通过树脂层彼此接合。 因此，适当地增强了电子器件与绝缘基片之间的接合强度。

公开(公告)号：US07280372B2

公开(公告)日：2007-10-09

申请号：US10990280

申请日：2004-11-15

Applicant: Kevin P. Grundy ,  William F. Wiedemann ,  Joseph C. Fjelstad

Inventor： Kevin P. Grundy ,  William F. Wiedemann ,  Joseph C. Fjelstad

IPC: H05K1/11

CPC classification number: H05K3/3405 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/183 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10727 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Disclosed are stair stepped PCB structures which provide high performance, direct path, via-less interconnections between various elements of an electronic interconnection structure including, among others, IC packages and connectors.

Abstract translation: 公开了楼梯级PCB结构，其提供包括IC封装和连接器在内的电子互连结构的各种元件之间的高性能，直接路径，无通孔互连。

公开(公告)号：US20070228557A1

公开(公告)日：2007-10-04

申请号：US11715345

申请日：2007-03-08

Applicant: Shinya Onodera ,  Mikio Tsuruoka

Inventor： Shinya Onodera ,  Mikio Tsuruoka

IPC: H01L23/48

CPC classification number: H05K3/323 ,  H01C1/01 ,  H01C1/148 ,  H01C7/18 ,  H01G2/06 ,  H01G4/228 ,  H01G4/30 ,  H01L2224/32225 ,  H05K2201/10727

Abstract: An electronic component is comprised of an element body having at least one plane, and a terminal electrode to be electrically connected through an electroconductive particle to a circuit substrate. The terminal electrode is formed on the plane of the element body. When the plane of the element body is defined as a reference plane, a ratio of a projected area onto the reference plane of an external surface of the terminal electrode opposed to the circuit substrate in a region where a height of the terminal electrode from the reference plane is not less than a value resulting from subtraction of a diameter of the electroconductive particle from a maximum of the height, to a projected area onto the reference plane of the external surface of the terminal electrode opposed to the circuit substrate is set to be not less than 10%.

Abstract translation: 电子部件由具有至少一个平面的元件主体和通过导电粒子与电路基板电连接的端子电极构成。 端子电极形成在元件体的平面上。 当元件体的平面被定义为参考平面时，在终端电极的高度与参考电极的区域中的投影面积与端子电极的与电路基板相对的外表面的参考平面的比率 平面不小于从最大高度减去导电颗粒的直径到与电路基板相对的端子电极的外表面的参考平面上的投影面积的值不是 小于10％。

公开(公告)号：US20070201215A1

公开(公告)日：2007-08-30

申请号：US11703660

申请日：2007-02-08

Applicant: Atsushi Ito ,  Takayoshi Honda

Inventor： Atsushi Ito ,  Takayoshi Honda

IPC: H05K7/00

CPC classification number: H05K1/111 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K1/114 ,  H05K3/341 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09709 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: In an electronic device, a QFN is surface-mounted on a printed board. The QFN includes a main body containing an IC chip, a reinforcement portion, and multiple terminal portions. The reinforcement portion is exposed from a bottom portion of the main body and mechanically coupled with multiple reinforcement lands on the printed board. The multiple terminal portions are exposed from a peripheral of the main body and electrically coupled with multiple lands on the printed board. In the printed board, the multiple lands are connected with multiple conductive wires. Some of the multiple conductive wires are outside of the surface-mounted area. The others are inside of the surface-mounted area to face the reinforcement lands. This enhances a mounting efficiency in the printed board.

Abstract translation: 在电子设备中，QFN被表面安装在印刷电路板上。 QFN包括一个包含IC芯片的主体，加强部分和多个端子部分。 加强部分从主体的底部暴露并与印刷板上的多个加强筋机械连接。 多个端子部分从主体的外围露出并与印刷电路板上的多个焊盘电耦合。 在印刷电路板上，多个焊盘与多条导线连接。 多个导线中的一些位于表面安装区域的外部。 其他的是在表面安装区域的内部，以面对加固区域。 这提高了印刷电路板的安装效率。

公开(公告)号：US20070200252A1

公开(公告)日：2007-08-30

申请号：US11710841

申请日：2007-02-26

Applicant: Kenji Kaji

Inventor： Kenji Kaji

IPC: H01L23/48

CPC classification number: H05K3/3442 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09181 ,  H05K2201/09781 ,  H05K2201/10727 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

Abstract: According to one embodiment, a circuit board apparatus includes a substrate mounting a semiconductor component. A circuit board mounts the substrate. A solder bonding portion is provided in a side surface of the substrate. A pad is provided on the circuit board and solder bonded to the solder bonding portion.

Abstract translation: 根据一个实施例，电路板装置包括安装半导体部件的基板。 电路板安装基板。 焊接接合部设置在基板的侧面。 焊盘设置在电路板上并焊接到焊接部分上。

公开(公告)号：US20070151757A1

公开(公告)日：2007-07-05

申请号：US11687319

申请日：2007-03-16

Applicant: Katsuhiko FUJIKAWA ,  Koji TANAKA

Inventor： Katsuhiko FUJIKAWA ,  Koji TANAKA

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/111 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09663 ,  H05K2201/10075 ,  H05K2201/10727 ,  Y02P70/611

Abstract: A wiring board module includes a multilayer wiring board. A crystal oscillator and an IC component, for example, are mounted on the mounting surface of the multilayer wiring board. Mounting lands for the IC component, mounting lands for the crystal oscillator, and mounting lands for other surface mount components are provided on the mounting surface. Each mounting land for the crystal oscillator is not a conventional single large-area land but is defined by four adjacent land pieces. The four land pieces are electrically connected via an external terminal of the crystal oscillator, thereby functioning as a mounting land for the external terminal. In other words, each of the plurality of mounting lands provided at locations corresponding to external terminals of the crystal oscillator is divided into four land pieces.

Abstract translation: 布线板模块包括多层布线板。 例如，在多层布线基板的安装面上安装有晶体振荡器和IC部件。 在安装面上设有用于IC部件的安装平台，晶体振荡器的安装平台和其他表面安装部件的安装台面。 用于晶体振荡器的每个安装平台不是常规的单个大面积的土地，而是由四个相邻的陆块限定。 四块焊盘通过晶体振荡器的外部端子电连接，从而用作外部端子的安装焊盘。 换句话说，设置在与晶体振荡器的外部端子对应的位置处的多个安装焊盘中的每一个被分成四个焊盘。

公开(公告)号：US07226809B2

公开(公告)日：2007-06-05

申请号：US10440590

申请日：2003-05-19

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

IPC: H01L21/44

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract translation: 多芯片组件包括在其外围边缘上具有外部连接器的半导体器件或半导体器件部件。 外部连接器通过沿相邻的未切割半导体器件或半导体器件部件之间的边界线形成通孔而形成，然后用导电材料电镀或填充孔。 当相邻的半导体器件或半导体器件部件彼此切断时，半导体器件之间的每个通孔中的导电材料被二等分。 多芯片组件的半导体器件和组件可以具有不同的尺寸，以及具有不同直径和间距的外部连接器阵列。 每个外部连接器的一端或两端可以电连接到另一个对准的外部连接器或另一个半导体器件或组件的接触区域。 以这种方式组装提供了低调的堆叠组件。