公开(公告)号：US06806562B2

公开(公告)日：2004-10-19

申请号：US10057127

申请日：2002-01-25

Applicant: Bernd Barchmann ,  Erik Heinemann ,  Josef Heitzer ,  Frank Pueschner

Inventor： Bernd Barchmann ,  Erik Heinemann ,  Josef Heitzer ,  Frank Pueschner

IPC: H01L2302

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73203 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81898 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/113 ,  H05K3/325 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2201/209 ,  H01L2224/05639 ,  H01L2924/00014

Abstract: A device having a semiconductor component and a printed circuit board are described. The semiconductor component has external contacts and the printed circuit board has contact terminals. The contact terminals display a central blind opening, into which the external contacts of the semiconductor component protrude and are in a force-locking engagement with the contact terminal areas. In the method of electromechanically connecting the two parts to form a device, after they have been aligned, the two components are merely pressed onto each other.

Abstract translation: 描述具有半导体部件和印刷电路板的器件。 半导体元件具有外部触点，并且印刷电路板具有接触端子。 接触端子显示中央盲孔，半导体部件的外部触点突出并且与接触端子区域形成力锁定接合。 在机电地连接两部分以形成装置的方法中，在它们对准之后，两个部件仅被压在彼此上。

公开(公告)号：US06323432B1

公开(公告)日：2001-11-27

申请号：US09371290

申请日：1999-08-10

Applicant: Jeffrey S. Campbell ,  William T. Wike

Inventor： Jeffrey S. Campbell ,  William T. Wike

IPC: H01R909

CPC classification number: H01R13/2414 ,  F28F2215/10 ,  F28F2245/06 ,  H01L23/3733 ,  H01L23/49811 ,  H01L2224/29499 ,  H01L2924/0002 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/10977 ,  H05K2201/209 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10S117/903 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A technique for making acicular, branched, conductive dendrites, and a technique for using the dendrites to form a conductive compressible pad-on-pad connector are provided. To form the dendrites, a substrate is provided on which dendrites are grown, preferably on a metal film. The dendrites are then removed from the substrate, preferably by etching metal from the substrate. The so formed dendrites are incorporated into a compressible dielectric material, which then forms a compressible pad-on-pad connector between two conducting elements, such as connector pads on electrical devices, e.g. an I/C chip mounted on a substrate, such as a chip carrier.

Abstract translation: 提供了一种用于制造针状，分枝，导电树突的技术，以及使用树突形成导电可压缩垫片连接器的技术。 为了形成枝晶，提供在其上生长树突的基底，优选在金属膜上。 然后，优选通过从衬底中蚀刻金属，从树脂上除去树突。 如此形成的树突被并入到可压缩电介质材料中，其然后在两个导电元件之间形成可压缩垫片连接器，例如电气设备上的连接器焊盘，例如电连接器。 安装在诸如芯片载体的基板上的I / C芯片。

公开(公告)号：US5172473A

公开(公告)日：1992-12-22

申请号：US765299

申请日：1991-09-25

Applicant: Francis C. Burns ,  John J. Kaufman ,  David E. King ,  Alan D. Knight

Inventor： Francis C. Burns ,  John J. Kaufman ,  David E. King ,  Alan D. Knight

IPC: H01L23/32 ,  H01R4/58 ,  H01R13/03 ,  H01R43/16 ,  H05K3/00 ,  H05K3/32 ,  H05K3/36 ,  H05K3/40

CPC classification number: H01L23/32 ,  H01R4/58 ,  H01R43/16 ,  H05K3/325 ,  H05K3/4007 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R13/03 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/209 ,  H05K2203/0307 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/365 ,  Y10S430/146 ,  Y10T29/49224

Abstract: A method of making an electrical contact comprised of at least one, and preferably several, conical projections, is provided. The individual conical projections are comprised of an ablative material, and at least some of the conical projections include a surface which is substantially comprised of material in a thickness capable of making ohmic contact, either by wiping with an intermeshing like structure or by contacting a substantially flat contact pad. An interconnection, in this invention, is the combination of at least one contact having individual conical projections and another contact, optionally having individual conical projections. The conical projections are formed by laser. The conical projections are optionally formed on the head of a contact pin.

Abstract translation: 提供了由至少一个，优选几个锥形突起构成的电接触的方法。 各个锥形突起由可烧蚀材料组成，并且至少一些锥形突起包括基本上由能够进行欧姆接触的厚度的材料构成的表面，或者通过用相互啮合的结构擦拭或者通过基本上接触 平面接触垫。 在本发明中的互连是至少一个具有单独的锥形突起的接触件和另一个接触件的组合，可选地具有单独的锥形突出部。 锥形突起由激光形成。 锥形突起可选地形成在接触销的头部上。

公开(公告)号：US20190200683A1

公开(公告)日：2019-07-04

申请号：US16192912

申请日：2018-11-16

Applicant: Wearable Technology Limited

Inventor： Michael John Lynch

IPC: A41D1/00 ,  H05K1/14 ,  H05K3/36 ,  H05K3/28 ,  H01R12/71 ,  H01R12/62 ,  H01R43/20 ,  H01R13/58 ,  H01R13/516 ,  A41D1/04 ,  A41D3/00

CPC classification number: A41D1/002 ,  A41D1/04 ,  A41D3/00 ,  H01B3/46 ,  H01B7/0846 ,  H01R12/62 ,  H01R12/716 ,  H01R13/516 ,  H01R13/5845 ,  H01R13/622 ,  H01R43/205 ,  H05K1/142 ,  H05K3/28 ,  H05K3/368 ,  H05K2201/10356 ,  H05K2201/209 ,  H05K2203/1327

Abstract: An electrical connector having a detachable interface and a permanent interface is supported by connecting the permanent interface to a circuit-board. A first loom end (303) and a second loom end (305) are connected to the circuit board and an over-moulding (404) is applied to cover the permanent interface, the first loom end and the second loom end. The detachable interface is located through an orifice in an item of clothing (410) and the over-moulding is secured to an internal surface of an item of clothing by a first side flange (404) and a second side flange (405).

公开(公告)号：US09759405B2

公开(公告)日：2017-09-12

申请号：US15132243

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Ho Shin ,  Seok Chan Hong ,  Sung Oh Ahn

IPC: F21V13/04 ,  H01L33/60 ,  H05K3/00 ,  F21K9/60 ,  F21V5/04 ,  F21V7/05 ,  G02F1/1335

CPC classification number: F21V13/04 ,  F21K9/60 ,  F21V5/04 ,  F21V7/05 ,  G02F1/133611 ,  H01L33/60 ,  H05K3/0052 ,  H05K2201/0108 ,  H05K2201/10106 ,  H05K2201/2054 ,  H05K2201/209

Abstract: A light emitting module includes a circuit board having a plurality of reflective portions arranged in one direction and connection portions connecting the plurality of reflective portions, light emitting devices mounted on the plurality of reflective portions, and lens units disposed to cover the light emitting devices within boundaries of surfaces, of the plurality of reflective portions, on which the light emitting devices are mounted. A width of each of the connection portions in the other direction, perpendicular to the one direction thereof, is smaller than a diameter of each of the lens units, thus reducing a generation of a dark portion.

公开(公告)号：US09350124B2

公开(公告)日：2016-05-24

申请号：US14408039

申请日：2013-03-13

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： James Rathburn

IPC: H01R12/68 ,  H01R12/50 ,  H01R13/24 ,  H01R12/82 ,  H05K3/36 ,  H05K3/40 ,  H01R12/73 ,  H01L23/00 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。

公开(公告)号：US09062857B2

公开(公告)日：2015-06-23

申请号：US13090702

申请日：2011-04-20

Applicant: Yontae Moon ,  Eunseon Lee

Inventor： Yontae Moon ,  Eunseon Lee

IPC: H01R33/00 ,  F21V19/00 ,  F21K99/00 ,  F21V21/35 ,  F21Y101/02 ,  H01L33/48 ,  F21Y111/00

CPC classification number: F21V19/0045 ,  F21K9/00 ,  F21K9/275 ,  F21V19/001 ,  F21V19/0015 ,  F21V19/003 ,  F21V21/35 ,  F21Y2107/30 ,  F21Y2115/10 ,  H01L33/486 ,  H01L2224/48091 ,  H05K1/182 ,  H05K3/30 ,  H05K2201/10106 ,  H05K2201/2027 ,  H05K2201/209 ,  H05K2203/167 ,  H01L2924/00014

Abstract: A light emitting device module is provided comprising a light emitting device package and a printed circuit board to which the light emitting device package is coupled, wherein the light emitting device package includes a sliding groove and a fixing groove, and wherein the printed circuit board includes a sliding protrusion coupled to the sliding groove to guide the light emitting device package to a predetermined position and a fixing protrusion coupled to the fixing groove at the predetermined position.

Abstract translation: 提供一种发光器件模块，包括发光器件封装和耦合发光器件封装的印刷电路板，其中发光器件封装包括滑动槽和固定槽，并且其中印刷电路板包括 滑动突起，其联接到所述滑动槽以将所述发光器件封装引导到预定位置;以及固定突起，其在所述预定位置处联接到所述固定槽。

公开(公告)号：US20150136467A1

公开(公告)日：2015-05-21

申请号：US14408039

申请日：2013-03-13

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： James Rathburn

IPC: H01R12/77 ,  H01R12/82 ,  H01R12/79

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。

公开(公告)号：US20140133110A1

公开(公告)日：2014-05-15

申请号：US14076586

申请日：2013-11-11

Applicant: IBIDEN CO., LTD.

Inventor： Michimasa TAKAHASHI ,  Teruyuki ISHIHARA

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K1/14 ,  H05K1/183 ,  H05K3/0097 ,  H05K2201/068 ,  H05K2201/09145 ,  H05K2201/209 ,  H05K2203/0169

Abstract: A combined wiring board has multiple piece components each including a wiring board, and a frame component having an accommodation opening portion and holding the multiple piece components in the accommodation opening portion such that each of the piece components is fixed to the frame component at an outer rim of each of the piece components. The frame component has a thermal expansion coefficient in a planar direction which is set higher than a thermal expansion coefficient of the multiple piece components in the planar direction.

Abstract translation: 组合电路板具有多个片状部件，每个部件包括布线板和具有容纳开口部分的框架部件，并且将多个部件保持在容纳开口部分中，使得每个零件部件在外部固定到框架部件 每个零件的边缘。 框架部件在平面方向上具有比多个部件在平面方向上的热膨胀系数高的热膨胀系数。

公开(公告)号：US20130244490A1

公开(公告)日：2013-09-19

申请号：US13879883

申请日：2011-11-29

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R31/06 ,  H05K3/12 ,  H05K3/10

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. The electrical interconnect includes a socket substrate with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are bonded to the first surface of the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias are located in the openings that electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pad that are adapted to electrically and mechanically couple the electrical interconnect to the PCB.

Abstract translation: 适于在BGA器件上的焊球和PCB之间提供界面的表面贴装电互连。 电互连包括具有第一表面，第二表面和多个开口的插座基板，其尺寸和构造用于接收BGA器件上的焊球。 多个导电接触片接合到插座衬底的第一表面，使得接触片上的接触尖端延伸到开口中。 当焊球定位在开口中时，接触尖端与BGA器件电耦合。 通孔位于开口中，其将接触片电耦合到位于插座衬底的第二表面附近的接触垫。 焊球被接合到接触焊盘上，适于电连接和机械地将电互连件耦合到PCB。