公开(公告)号：US20240339443A1

公开(公告)日：2024-10-10

申请号：US18401694

申请日：2024-01-01

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/167 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/83

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a first package including a first redistribution layer, at least one chip and a second redistribution layer, and at least one second package disposed on the first package and including a substrate, an adhesive layer, at least two optical chips, an encapsulant layer, and a third redistribution layer. The optical chips are attached to a surface of the substrate close to the first package through the adhesive layer, and each optical chip has an optical surface close to the substrate. The encapsulant layer is disposed on the surface and surrounds the optical chips. The third redistribution layer is disposed between the encapsulant layer and the second redistribution layer, in which the second redistribution layer is electrically connected to the optical chips through the third redistribution layer.

公开(公告)号：US20230110079A1

公开(公告)日：2023-04-13

申请号：US17821168

申请日：2022-08-20

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Pei-chun Tsai ,  Hung-hsin Hsu ,  Ching-wei Liao ,  Shang-yu Chang Chien

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A fan-out package structure and a manufacturing method thereof are provided. The fan-out package structure includes an upper redistribution layer, a die, a passive element, and an active element. The upper redistribution layer includes a first surface and a second surface opposite to the first surface. The die is disposed on the first surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The passive element is disposed on the second surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The active element is disposed on the second surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The active element is laterally adjacent to the passive element, and the die is electrically connected to the active element and the passive element through the upper redistribution layer.

公开(公告)号：US11532575B2

公开(公告)日：2022-12-20

申请号：US16562442

申请日：2019-09-06

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/78 ,  H01L23/552

Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US20220320063A1

公开(公告)日：2022-10-06

申请号：US17407174

申请日：2021-08-19

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Pei-Hsun Chou ,  Ko-Lun Liao

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A package structure and a manufacturing thereof are provided. The package structure includes a base, a chip, a control element and an underfill. The chip is disposed on the base and includes a recess, and the recess has a bottom surface and a sidewall. The control element is disposed between the base and the chip and disposed on the bottom surface of the recess, and a gap exists between the control element and the sidewall of the recess. The underfill is disposed in the recess. The chip and the control element are electrically connected to the base respectively.

公开(公告)号：US20220302061A1

公开(公告)日：2022-09-22

申请号：US17392369

申请日：2021-08-03

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu CHANG-CHIEN ,  Hung-Hsin HSU ,  Nan-Chun LIN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/463 ,  H01L23/488

Abstract: A semiconductor package and fabricating method thereof are disclosed. The semiconductor package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first area. The pads are formed on a first area of the active surface. Each first bump is formed on the corresponding pad. The second bumps are formed on the second area and each second bump has a first layer and a second layer with different widths. The encapsulation encapsulates the chip and the first and second bumps and is ground to expose the first and second bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased.

公开(公告)号：US11410945B2

公开(公告)日：2022-08-09

申请号：US17094101

申请日：2020-11-10

Applicant: Powertech Technology Inc.

Inventor： Shih-Chun Chen ,  Sheng-Tou Tseng ,  Kun-Chi Hsu ,  Chin-Ta Wu ,  Ying-Lin Chen ,  Ting-Yeh Wu

IPC: H01L23/66 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01Q1/22

Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.

公开(公告)号：US11309296B2

公开(公告)日：2022-04-19

申请号：US16687713

申请日：2019-11-19

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Wen-Hsiung Chang

IPC: H01L25/16 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

公开(公告)号：US20220013486A1

公开(公告)日：2022-01-13

申请号：US17149835

申请日：2021-01-15

Applicant: Powertech Technology Inc.

Inventor： Shih-Chang HUANG ,  Yu-Cheng LIU

IPC: H01L23/00

Abstract: A semiconductor composite structure includes an electrically conductive bump, and a patterned bonding layer. The electrically conductive bump includes a body portion for being electrically connected to a metal layer of a semiconductor substrate, and a contact portion disposed on the body portion opposite to the metal layer. The patterned bonding layer is disposed on the contact portion opposite to the body portion, and includes an electrically conductive portion and a recess portion depressed relative to the electrically conductive portion. An etching selectivity ratio of the conductive portion relative to the contact portion is greater than 1. A method for making the semiconductor composite structure and a semiconductor device are also disclosed.

公开(公告)号：US20210257231A1

公开(公告)日：2021-08-19

申请号：US16920409

申请日：2020-07-02

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Shinichi Sakurada

IPC: H01L21/67 ,  H01L21/683

Abstract: A semiconductor manufacturing apparatus includes a supporting stage for mounting a semiconductor wafer with a protective member attached thereto, a pressing device for pressing the semiconductor wafer with a protective member attached thereto, an ultraviolet irradiation device, and a chamber for housing the supporting stage, the pressing device, and the ultraviolet irradiation device. The pressing device includes an ultraviolet transmitting plate. The pressing device drives the ultraviolet transmitting plate to generate a pressing force for pressing the semiconductor wafer with a protective member attached thereto on a supporting stage. The pressing device is moved relatively to the supporting stage such that the semiconductor wafer and the protective member are sandwiched between the ultraviolet transmitting plate and the supporting stage. The ultraviolet rays emitted from the ultraviolet irradiation device pass through the ultraviolet transmitting plate and are irradiated to the protective member.

公开(公告)号：US20210217632A1

公开(公告)日：2021-07-15

申请号：US17094537

申请日：2020-11-10

Applicant: Powertech Technology Inc.

Inventor： Shih-Chun CHEN ,  Sheng-Tou TSENG ,  Kun-Chi HSU ,  Chin-Ta WU ,  Ting-Yeh WU

IPC: H01L21/56 ,  H01L23/552

Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.