公开(公告)号：US20240027488A1

公开(公告)日：2024-01-25

申请号：US18255501

申请日：2021-10-21

Applicant: SEMICONDUCTOR MANUFACTURING ELECTRONICS (SHAOXING) CORPORATION

Inventor： Zhaolin ZHANG ,  Jihui XU

IPC: G01P15/08 ,  G01P15/125 ,  B81C1/00

CPC classification number: G01P15/0802 ,  G01P15/125 ,  B81C1/00166 ,  B81C2201/0125 ,  B81C2201/0132

Abstract: In a forming method of an inertial sensor, a trench is formed in a conducting material layer, so that a formed movable comb tooth structure can be spaced from the conducting material layer. A thin film layer is further arranged at a bottom of the trench. The thin film layer can be used not only for realizing etching blocking, but also for fixing comb teeth of the movable comb tooth structure while executing an etching process for forming the movable comb tooth structure, thereby avoiding damage to side walls of the comb teeth due to torsion of the comb teeth. In addition, a thickness of the thin film layer can be made small, and correspondingly, the thin film layer can be removed by a small etching amount, without causing a large amount of erosion to other film layers, which is conducive to guaranteeing stability of modules in a device.

公开(公告)号：US20230357000A1

公开(公告)日：2023-11-09

申请号：US17811109

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Jung Chen

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81B2203/04 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  B81C2201/0176

Abstract: A membrane is formed through processes including depositing a first piezoelectrical layer, depositing a first electrode layer over the first piezoelectrical layer, patterning the first electrode layer to form a first electrode, depositing a second piezoelectrical layer over the first electrode, depositing a second electrode layer over the second piezoelectrical layer, patterning the second electrode layer to form a second electrode, and depositing a third piezoelectrical layer over the second electrode. The third piezoelectrical layer, the second piezoelectrical layer, and the first piezoelectrical layer are etched to form a through-hole. The through-hole is laterally spaced apart from the first electrode and the second electrode. A first contact plug and a second contact plug are then formed to electrically connect to the first electrode and the second electrode, respectively.

公开(公告)号：US20180362335A1

公开(公告)日：2018-12-20

申请号：US16058897

申请日：2018-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JUNG-HUEI PENG ,  CHIA-HUA CHU ,  FEI-LUNG LAI ,  SHIANG-CHI LIN

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/0038 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/012 ,  B81C1/00285 ,  B81C2201/0125 ,  B81C2201/0154 ,  B81C2201/019 ,  B81C2203/0118 ,  B81C2203/035 ,  B81C2203/0792

Abstract: The present disclosure provides a CMOS structure, including a substrate, a metallization layer over the substrate, a sensing structure over the metallization layer, and a signal transmitting structure adjacent to the sensing structure. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier over the outgassing layer; and an electrode over the patterned outgassing barrier. The signal transmitting structure electrically couples the electrode and the metallization layer.

公开(公告)号：US09932222B2

公开(公告)日：2018-04-03

申请号：US15162994

申请日：2016-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00 ,  G06F17/50 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

公开(公告)号：US20180086632A1

公开(公告)日：2018-03-29

申请号：US15704537

申请日：2017-09-14

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Joachim Mahler ,  Daniel Porwol ,  Alfred Sigl

IPC: B81C1/00

CPC classification number: B81C1/00047 ,  B81C1/00666 ,  B81C2201/0125 ,  B81C2201/013 ,  B81C2203/0118 ,  B81C2203/0127

Abstract: A method for fabricating an electronic device is disclosed. In one example, the method comprises providing a semiconductor wafer, forming a plurality of cavities into the semiconductor wafer, filling a stabilization material into the cavities, fabricating a temporary panel by applying a cap sheet onto the semiconductor wafer, the cap sheet covering the cavities, singulating the temporary panel into a plurality of semiconductor devices, fabricating an embedded wafer by embedding the semiconductor devices in an encapsulant, removing the cap sheet of each one of the semiconductor devices, and singulating the embedded wafer into a plurality of electronic devices.

公开(公告)号：US20170107099A1

公开(公告)日：2017-04-20

申请号：US14883908

申请日：2015-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JUNG-HUEI PENG ,  CHIA-HUA CHU ,  FEI-LUNG LAI ,  SHIANG-CHI LIN

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  B81B7/0038 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/012 ,  B81C1/00285 ,  B81C2201/0125 ,  B81C2201/0154 ,  B81C2201/019 ,  B81C2203/0118 ,  B81C2203/035 ,  B81C2203/0792

Abstract: The present disclosure provides a CMOS structure, including a substrate, a metallization layer over the substrate, a sensing structure over the metallization layer, and a signal transmitting structure adjacent to the sensing structure. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier over the outgassing layer; and an electrode over the patterned outgassing barrier. The signal transmitting structure electrically couples the electrode and the metallization layer.

公开(公告)号：US20170015548A1

公开(公告)日：2017-01-19

申请号：US14963362

申请日：2015-12-09

Applicant: Texas Instruments Incorporated

Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

Abstract translation: 一种以面板格式制造具有开口腔（110a）的封装半导体器件（100）的方法; 将具有平垫（230）和对称放置的垂直柱（231）的金属片的面板尺寸网格放置（处理201）在粘合剂载带上。 将具有传感器系统的半导体芯片（工艺202）面朝下地附接到带上; 层压（工艺203）和减薄（工艺204）低CTE绝缘材料（234）以填充芯片和网格之间的间隙; 翻转（过程205）组装以去除胶带; 等离子体清洁组件正面，溅射和图案化（工艺206）跨组合均匀的金属层和任选的电镀（工艺209）金属层以形成重新布线迹线和扩展的接触垫用于组装; 层压（工艺212）跨板的绝缘加强件; 在加强件中打开（过程213）空腔以接近传感器系统; 并通过切割金属片来分割（处理214）包装的装置。

公开(公告)号：US20160157038A1

公开(公告)日：2016-06-02

申请号：US15018625

申请日：2016-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Huei Peng ,  Chia-Hua Chu ,  Chun-wen Cheng ,  Chin-Yi Cho ,  Li-Min Hung ,  Yao-Te Huang

IPC: H04R31/00 ,  B81C1/00

CPC classification number: H04R31/003 ,  B81C1/00158 ,  B81C2201/0125 ,  B81C2201/013 ,  B81C2201/053 ,  B81C2203/036 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2307/027

Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

Abstract translation: 本公开提供了集成麦克风结构的一个实施例。 集成麦克风结构包括图案化为第一板的第一硅衬底。 形成在第一硅衬底的一侧上的氧化硅层。 第二硅衬底通过氧化硅层与第一衬底结合，使得氧化硅层夹在第一和第二硅衬底之间。 一个膜片，其固定在氧化硅层上并且设置在第一和第二硅衬底之间，使得第一板和隔膜被配置成形成电容式麦克风。

公开(公告)号：US20140308771A1

公开(公告)日：2014-10-16

申请号：US13861620

申请日：2013-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00 ,  G06F17/50

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Abstract translation: 公开了微机电系统（MEMS）结构，制造方法和设计结构。 该方法包括通过在MEMS光束上方和下方排出钨材料和硅材料来形成微电子机械系统（MEMS）光束结构，以在MEMS光束上方形成上腔体，并在MEMS光束下方形成下腔体结构。

公开(公告)号：US08236694B2

公开(公告)日：2012-08-07

申请号：US12884823

申请日：2010-09-17

Applicant: Jyrki Kiihamäki ,  Hannu Kattelus

Inventor： Jyrki Kiihamäki ,  Hannu Kattelus

IPC: H01L21/302

CPC classification number: B81C1/00611 ,  B81C2201/0125

Abstract: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap.

Abstract translation: 本发明涉及加速度传感器的制造方法。 在该方法中，使用薄SOI晶片结构，其中蚀刻凹槽，其壁被氧化。 覆盖所有其他材料的厚电极材料层生长在结构的顶部，然后将表面研磨并化学机械地抛光，在结构中蚀刻薄的释放孔，形成结构图案，最后使用 执行氢氟酸溶液以释放旨在移动并打开电容间隙的结构。