公开(公告)号：US07230506B2

公开(公告)日：2007-06-12

申请号：US10682617

申请日：2003-10-09

Applicant: William Beale ,  John T. Stonick ,  Jeffrey L. Sonntag

Inventor： William Beale ,  John T. Stonick ,  Jeffrey L. Sonntag

IPC: H01P3/04

CPC classification number: H05K1/0245 ,  H01P3/02 ,  H05K1/0228 ,  H05K1/0248 ,  H05K1/115 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263

Abstract: A technique is presented for minimizing crosstalk between adjacent differential signal pairs in communications. A backplane embodiment wherein the backplane includes a plurality of differential signal line pairs, is presented. A first differential signal line pair can include a first differential signal line and a second differential signal line. The backplane can have the first differential signal line connected between first and second vias. The second differential signal line can be connected between third and fourth vias. A third signal line can be connected between fifth and sixth vias. The first via can be spatially adjacent to the fifth via such that a signal on the third signal line is coupled to the first differential signal line and the fourth via can be spatially located adjacent to the sixth via such that a signal on the third signal line is coupled to the second differential signal line.

Abstract translation: 提出了一种用于最小化通信中相邻差分信号对之间的串扰的技术。 提出了背板实施例，其中背板包括多个差分信号线对。 第一差分信号线对可以包括第一差分信号线和第二差分信号线。 背板可以具有连接在第一和第二通孔之间的第一差分信号线。 第二差分信号线可以连接在第三和第四通孔之间。 第三个信号线可以连接在第五和第六个通孔之间。 第一通孔可以在空间上与第五通孔相邻，使得第三信号线上的信号耦合到第一差分信号线，并且第四通孔可以在空间上位于第六通孔附近，使得第三信号线上的信号 耦合到第二差分信号线。

公开(公告)号：US20070130555A1

公开(公告)日：2007-06-07

申请号：US11601734

申请日：2006-11-20

Applicant: Hideki Osaka

Inventor： Hideki Osaka

IPC: G06F17/50 ,  H03K17/693

CPC classification number: H05K1/0216 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/08 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0298 ,  H05K2201/0352 ,  H05K2201/044 ,  H05K2201/09236 ,  H01L2924/00

Abstract: In the case where high speed differential signals are transmitted in differential transmission lines through via holes with open-stubs, signal waveforms are distorted due to impedance mismatch in the open-stubs of the via holes, thus causing jitter, which has become an issue of high speed signals. For differential transmission lines that pass through via holes with open-stubs, a degree of coupling of the lines is decreased while the differential characteristic impedance is made constant. Thereby, the effects of backward cross talk noise caused by the coupling can be minimized, and thus jitter can be suppressed.

Abstract translation: 在差分传输线路中通过具有开路短路的通孔传输高速差分信号的情况下，由于通孔的开路短路中的阻抗失配，信号波形失真，从而引起抖动，这已成为问题 高速信号。 对于通过具有开路短路的通孔的差分传输线，线路的耦合度降低，同时使差分特性阻抗恒定。 由此，由耦合引起的后向串扰噪声的影响可以最小化，从而可以抑制抖动。

公开(公告)号：US20070128896A1

公开(公告)日：2007-06-07

申请号：US11296632

申请日：2005-12-07

Applicant: Dan Willis ,  David Kraus

Inventor： Dan Willis ,  David Kraus

IPC: H05K1/00

CPC classification number: H05K1/116 ,  H01R12/7023 ,  H01R12/716 ,  H01R12/721 ,  H05K1/0237 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09409 ,  H05K2201/10189

Abstract: According to some embodiments, a connector to receive a memory module includes a first row of a first plurality of interconnect ends, a second row of a second plurality of interconnect ends adjacent to the first row, and a third row of a third plurality of interconnect ends adjacent to the second row. An interconnect end of the first plurality of interconnect ends, an interconnect end of the second plurality of interconnect ends, and an interconnect end of the third plurality of interconnect ends may be substantially aligned.

Abstract translation: 根据一些实施例，用于接收存储器模块的连接器包括第一组第一多个互连端，邻近第一行的第二排第二多个互连端，以及第三排第三多个互连 在第二行附近结束。 第一多个互连端的互连端，第二多个互连端的互连端以及第三多个互连端的互连端可以基本上对齐。

公开(公告)号：US07206888B2

公开(公告)日：2007-04-17

申请号：US10626215

申请日：2003-07-24

Applicant: Charles Calvin Byers ,  Robert Allen Novotny

Inventor： Charles Calvin Byers ,  Robert Allen Novotny

IPC: G06F13/00

CPC classification number: H05K1/0296 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09236

Abstract: A novel backplane routing and configuration (200) supports a full mesh architecture. In this novel configuration, a circuit pack determines which backplane signals to use for a transmission based on the relative distance across the backplane between the board sending the communication and the board receiving the communication. Boards sending the same relative distance use the same rows of signals (204). That is, each row associated with the meshed interconnection is assigned a relative shift or distance for a connection. The rows (204) that represent a greater relative distance for shift between boards are intermixed next to rows (204) that have a relatively short distance between shifts or boards. In this manner, the number of layers required is minimized and the utilization of routing channels is optimized. In particular, for a N slot backplane with one routing channel between rows, (N/2+1) layers are required, rather than N layers. And, vertical routing is not required.

Abstract translation: 一种新颖的背板路由和配置（200）支持全网状架构。 在这种新颖的配置中，电路板基于发送通信的电路板和接收通信的电路板之间的背板之间的相对距离确定用于传输的背板信号。 发送相同相对距离的板使用相同的信号行（204）。 也就是说，与网状互连相关联的每一行被分配用于连接的相对移位或距离。 表示用于板之间移位的较大相对距离的行（204）被混合在行（204）之后，移位或板之间的距离相对较短。 以这种方式，所需的层数被最小化并且路由信道的利用被优化。 特别地，对于在行之间具有一个路由信道的N个时隙背板，需要（N / 2 + 1）层，而不是N层。 而且，不需要垂直路由。

公开(公告)号：US20070015409A1

公开(公告)日：2007-01-18

申请号：US11440069

申请日：2006-05-25

Applicant: Nicolas Imbert ,  Charles Chuc

Inventor： Nicolas Imbert ,  Charles Chuc

IPC: H01R13/648

CPC classification number: H05K7/1459 ,  H01R12/52 ,  H01R31/005 ,  H05K1/0289 ,  H05K1/14 ,  H05K1/148 ,  H05K7/1441 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09972

Abstract: A device (20) for interconnecting electrical bundles, includes a plurality of pluggable connection and cross-connect cards (34 to 38) for the electrical bundles. The device further includes a “main” printed circuit (28, 28b) fitted with connectors or slots (29 to 33) designed and arranged to receive the pluggable cards, the printed circuit having a plurality of parallel tracks (46), each enabling two tracks (61 to 63, 68) or tracks starters (70 to 72) provided respectively on two distinct pluggable cards plugged in the connectors of the main printed circuit to be put to the same potential, each of the parallel tracks (46) being in contact with a respective pin (50, 150) of a plurality of connectors of the main printed circuit.

Abstract translation: 用于互连电束的装置（20）包括用于电束的多个可插拔连接和交叉连接卡（34至38）。 该装置还包括装配有设计和布置成接收可插拔卡的连接器或槽（29至33）的“主”印刷电路（28,28b），印刷电路具有多个平行轨道（46），每个启用 两个轨道（61至63,68）或轨道起动器（70至72）分别设置在插入主印刷电路的连接器中以插入相同电位的两个不同的可插拔卡上，每个平行轨道（46）为 与主印刷电路的多个连接器的相应销（50,150）接触。

公开(公告)号：US07148428B2

公开(公告)日：2006-12-12

申请号：US10950827

申请日：2004-09-27

Applicant: Pascal C. H. Meier ,  Sanjay Dabral

Inventor： Pascal C. H. Meier ,  Sanjay Dabral

IPC: H05K1/16

CPC classification number: G06F1/189 ,  G06F1/184 ,  G06F1/185 ,  G06F1/186 ,  H01R12/79 ,  H05K1/14 ,  H05K1/147 ,  H05K3/222 ,  H05K3/305 ,  H05K2201/044 ,  H05K2201/10356 ,  H05K2201/10492 ,  H05K2201/10704 ,  H05K2201/2027 ,  Y10T29/49117

Abstract: A system and method are disclosed in which flex cables are affixed to PCBs, for providing high-speed signaling paths between ICs disposed upon the PCBs. The flex cables are fixably attached to the PCBs so as to substantially mimic their structural orientation. Where the configuration includes more than one PCB, the flex cables include multiple portions which are temporarily separable from one another and from the die, using flex-to-flex and flex-to-package connectors, allowing field maintenance of the configuration. By routing the high-speed signals between ICs onto the flex cable, single-layer PCBs can be used for non-critical and power delivery signals, at substantial cost savings. By disposing the flex cables onto the PCB rather than allowing the cables to float freely, the configuration is thermally managed as if the signals were on the PCB and cable routing problems are avoided.

Abstract translation: 公开了一种系统和方法，其中柔性电缆固定到PCB上，用于在布置在PCB上的IC之间提供高速信号路径。 柔性电缆可固定地连接到PCB，以便基本模拟其结构取向。 在配置包括多于一个PCB的情况下，柔性电缆包括可以使用柔性到柔性和挠性 - 包装连接器彼此临时分离和从模具临时分离的多个部分，从而允许现场维护配置。 通过将IC之间的高速信号路由到柔性电缆上，单层PCB可以用于非关键和电力传输信号，从而节省了大量成本。 通过将柔性电缆布置在PCB上，而不是允许电缆自由浮动，该配置将被热管理，就像信号在PCB上一样，避免了电缆布线问题。

公开(公告)号：US20060206647A1

公开(公告)日：2006-09-14

申请号：US11079627

申请日：2005-03-14

Applicant: Douglas Stahl ,  David Formisano ,  Andy Saffarian ,  Marwan Khoury

Inventor： Douglas Stahl ,  David Formisano ,  Andy Saffarian ,  Marwan Khoury

IPC: H05K7/10 ,  G06F13/00

CPC classification number: H05K1/14 ,  H05K1/144 ,  H05K2201/044 ,  H05K2201/045

Abstract: An Advanced Mezzanine Card (AMC) adapter may be used to connect a non-AMC mezzanine card to an AMC carrier. The AMC adapter may include a card edge connector configured to be connected to an AMC connector on the AMC carrier and one or more mezzanine connectors configured to be connected to the non-AMC mezzanine card. The AMC adapter may also include a bridge to convert between communication protocols used by the non-AMC mezzanine card and the AMC carrier. Of course, many alternatives, variations, and modification are possible without departing from this embodiment.

公开(公告)号：US07088711B2

公开(公告)日：2006-08-08

申请号：US10068616

申请日：2002-02-05

Applicant: Joel R. Goergen ,  Ashby Armistead ,  Greg Hunt

Inventor： Joel R. Goergen ,  Ashby Armistead ,  Greg Hunt

IPC: H04L12/50

CPC classification number: H05K1/0245 ,  H05K1/0228 ,  H05K1/0248 ,  H05K1/0298 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263

Abstract: A high-speed router backplane is disclosed. The disclosed construction and layout techniques enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that use signaling across the backplane at trace speeds of 2.5 Gbps or greater. Specific ranges of differential trace geometry characteristics, with significant single-ended coupling to adjacent ground planes, have been found to provide the parameters needed for such signaling. New trace routing and layering techniques also help in the realization of a backplane embodiment containing roughly 600 operable high-speed differential pairs, while also providing sufficient electromagnetic interference management to allow power distribution to occur within the same backplane.

公开(公告)号：US07085872B2

公开(公告)日：2006-08-01

申请号：US09839768

申请日：2001-04-19

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: H05K1/02

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

公开(公告)号：US20060105596A1

公开(公告)日：2006-05-18

申请号：US10988029

申请日：2004-11-12

Applicant: Steven Minich

Inventor： Steven Minich

IPC: H01R12/00

CPC classification number: H05K1/144 ,  H01R12/585 ,  H05K3/308 ,  H05K2201/044 ,  H05K2201/096 ,  H05K2201/10189 ,  H05K2201/1059

Abstract: A mid-plane is disclosed. The mid-plane includes a first printed circuit board having a plurality of plated vias adapted to receive tails attached to a first connector and having a plurality of unplated clearance holes adapted to receive tails attached to a second connector. The second printed circuit board has a plurality of plated vias adapted to receive tails attached to the second connector and has a plurality of unplated clearance adapted to receive tails attached to the first connector.

Abstract translation: 披露了一架中型飞机。 中间平面包括具有多个电镀通孔的第一印刷电路板，该电镀通孔适于接收连接到第一连接器的尾部，并且具有适于接收连接到第二连接器的尾部的多个未放置的间隙孔。 第二印刷电路板具有适于接收连接到第二连接器的尾部的多个电镀通孔，并且具有适于接收连接到第一连接器的尾部的多个未平坦的间隙。