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    WIRING BOARD
    65.
    发明申请
    WIRING BOARD 有权
    接线板

    公开(公告)号：US20120241197A1

    公开(公告)日：2012-09-27

    申请号：US13328351

    申请日：2011-12-16

    Applicant: Tetsuya HIRAOKA

    Inventor： Tetsuya HIRAOKA

    IPC: H05K1/02

    CPC classification number: H05K1/0271 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/0224 ,  H05K2201/09263 ,  H05K2201/09663 ,  H01L2924/00 ,  H01L2224/05599

    Abstract: A wiring board includes: a first wiring; a second wiring being disposed adjacently to the first wiring; a third wiring being disposed adjacently to the first wiring; a fourth wiring being disposed adjacently to the third wiring; and an insulating layer, wherein the second wiring and the fourth wiring are disposed adjacently to each other, the first wiring and the fourth wiring are not overlapped, the second wiring and the third wiring are not overlapped, a crest and a trough are provided on a side face of the first wiring, the crest and the trough are provided on a side face of the second wiring, the trough provided on the side face of the first wiring and the third wiring are overlapped, and the trough provided on the side face of the second wiring and the fourth wiring are overlapped.

    Abstract translation: 布线板包括：第一布线; 与所述第一布线相邻设置的第二布线; 与所述第一布线相邻设置的第三布线; 与第三布线相邻设置的第四布线; 以及绝缘层，其中所述第二布线和所述第四布线彼此相邻地布置，所述第一布线和所述第四布线不重叠，所述第二布线和所述第三布线不重叠，波峰和波谷设置在 第一布线的侧面，波峰和谷设置在第二布线的侧面上，设置在第一布线和第三布线的侧面上的槽重叠，并且设置在侧面上的槽 的第二布线和第四布线重叠。

    Printed circuit board strip and panel
    66.
    发明授权
    Printed circuit board strip and panel 有权
    印刷电路板条和面板

    公开(公告)号：US08253032B2

    公开(公告)日：2012-08-28

    申请号：US12761828

    申请日：2010-04-16

    Applicant: Ki-Gon Kim ,  Kwang-Seop Youm ,  Hyoung-Won Kang

    Inventor： Ki-Gon Kim ,  Kwang-Seop Youm ,  Hyoung-Won Kang

    IPC: H05K1/11

    CPC classification number: H05K3/242 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09263 ,  H05K2203/175 ,  H01L2924/00

    Abstract: A printed circuit board strip and a printed circuit board panel are disclosed. In accordance with an embodiment of the present invention, the printed circuit board strip includes an unit area, a plating lead-in wire, which is for plating the unit area, and a mold gate, which is disposed on an outer side of the unit area. Here, the plating lead-in wire and the mold gate are electrically connected to each other through a lead line having a shape that is bent plural times. This can significantly save the production cost by preventing an excessive plated layer from being formed in an unnecessary area.

    Abstract translation: 公开了印刷电路板条和印刷电路板面板。 根据本发明的实施例，印刷电路板条包括单元区域，用于电镀单元区域的电镀引入线，以及设置在单元的外侧上的模具门 区。 这里，电镀引入线和模具栅极通过多次弯曲形状的引线彼此电连接。 这可以通过防止在不必要的区域中形成过量的镀层来显着地节省生产成本。

    METHOD FOR GENERATING AN ELECTRONIC SYSTEM, METHOD FOR GENERATING A FREEFORM SURFACE HAVING SUCH A SYSTEM, AND ELECTRONIC SYSTEM AND FREEFORM SURFACES HAVING SUCH A SYSTEM
    67.
    发明申请
    METHOD FOR GENERATING AN ELECTRONIC SYSTEM, METHOD FOR GENERATING A FREEFORM SURFACE HAVING SUCH A SYSTEM, AND ELECTRONIC SYSTEM AND FREEFORM SURFACES HAVING SUCH A SYSTEM 有权
    用于生成电子系统的方法，用于产生具有这样的系统的FREEFORM表面的方法，以及具有这种系统的电子系统和FREEFORM表面

    公开(公告)号：US20120176764A1

    公开(公告)日：2012-07-12

    申请号：US13381552

    申请日：2010-06-29

    Applicant: Thomas Löher ,  Andreas Ostmann ,  Manuel Seckel

    Inventor： Thomas Löher ,  Andreas Ostmann ,  Manuel Seckel

    IPC: H05K7/00 ,  H05K3/36 ,  H05K13/04 ,  H05K3/30

    CPC classification number: H05K1/0283 ,  A41D1/005 ,  H05K1/038 ,  H05K1/189 ,  H05K3/284 ,  H05K2201/09263 ,  Y10T29/49126 ,  Y10T29/49146

    Abstract: The invention relates to a method for generating an electronic system for application to freeform surfaces, a method for producing freeform surfaces having an electronic system, and an electronic system and a combination of a freeform surface having at least one such system. According to the invention, an elastic interconnect device having an elastic substrate and an elastic, fanned-out contact structure with contact surfaces comprised of conductor lines is generated first. Then, electronic components are mounted on the interconnect device. Finally, the interconnect device is encapsulated. If a freeform surface with an electronic system is to be generated, the electronic system produced in this way is then mounted on the previously provided freeform surface.

    Abstract translation: 本发明涉及一种用于产生用于自由形成表面的电子系统的方法，一种用于生产具有电子系统的自由曲面的方法，以及电子系统以及具有至少一个这样的系统的自由曲面的组合。 根据本发明，首先产生具有弹性基板和具有由导体线构成的接触表面的弹性的扇形接触结构的弹性互连装置。 然后，电子部件安装在互连装置上。 最后，互连器件被封装。 如果要产生具有电子系统的自由曲面，则以这种方式制造的电子系统然后安装在先前提供的自由曲面上。

    Electronic device
    69.
    发明授权
    Electronic device 有权
    电子设备

    公开(公告)号：US08205105B2

    公开(公告)日：2012-06-19

    申请号：US13023491

    申请日：2011-02-08

    Applicant: Atsushi Nakamura ,  Toru Hayashi ,  Yuichi Mabuchi

    Inventor： Atsushi Nakamura ,  Toru Hayashi ,  Yuichi Mabuchi

    IPC: G06F1/00 ,  H05K1/03 ,  H05K9/00 ,  H04B3/28

    CPC classification number: H05K1/0233 ,  H01L2224/48247 ,  H05K1/0231 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/1003 ,  H05K2201/10189 ,  H05K2201/10689

    Abstract: An electronic device comprising: a wiring substrate having a first power-supply wiring to which a first power-supply potential is applied and a second power-supply wiring to which a second power-supply potential lower than the first power-supply potential is applied; a microcomputer having first and second power-supply terminals in which the first power-supply terminal is connected to the first power-supply wiring and the second power-supply terminal is connected to the second power-supply wiring; and a connector connected to the first and second power-supply wirings, wherein an inductor element for correcting an impedance error of the first and second wirings is connected in series to either one of the first and second power-supply wirings. According to such configuration, unnecessary electromagnetic radiation posed by a common current can be suppressed.

    Abstract translation: 一种电子设备，包括：布线基板，具有施加有第一电源电位的第一电源布线和施加低于所述第一电源电位的第二电源电位的第二电源布线 ; 具有第一和第二电源端子的微型计算机，其中第一电源端子连接到第一电源配线，第二电源端子连接到第二电源配线; 以及连接到第一和第二电源布线的连接器，其中用于校正第一和第二布线的阻抗误差的电感器元件串联连接到第一和第二电源布线中的任一个。 根据这种结构，可以抑制由公共电流引起的不必要的电磁辐射。

    Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at a Plurality of Memory Devices
    70.
    发明申请
    Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at a Plurality of Memory Devices 有权
    具有配置信号线的存储器模块，用于在多个存储器件上顺序到达信号

    公开(公告)号：US20120144085A1

    公开(公告)日：2012-06-07

    申请号：US13366191

    申请日：2012-02-03

    Applicant: Haw-Jyh Liaw ,  David Nguyen

    Inventor： Haw-Jyh Liaw ,  David Nguyen

    IPC: G06F13/40

    CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    Abstract: A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence.

    Abstract translation: 存储器模块包括衬底，多条信号线，时钟线和多个存储器件。 多条信号线包括彼此并行布置的第一和第二信号线，其中，对于第一和第二信号线中的每一条，从相应的第一边缘指状开始的相应信号依次穿过相应的第一段， 信号线，相应信号线的相应转弯部分以及相应信号线的相应第二部分。 时钟线是提供顺序穿过的时钟信号，第二边缘手指，时钟线的第一段，时钟线的转弯部分和时钟线的第二段。 相应的信号遍历并且时钟信号线依次到达多个存储器件。

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