公开(公告)号：US4710592A

公开(公告)日：1987-12-01

申请号：US875670

申请日：1986-06-18

Applicant: Kohji Kimbara

Inventor： Kohji Kimbara

IPC: H05K3/46 ,  H01L23/538 ,  H05K1/00 ,  H05K1/11 ,  H05K3/22 ,  H05K3/40

CPC classification number: H05K1/113 ,  H01L23/5382 ,  H05K1/0292 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/15192 ,  H05K1/0298 ,  H05K2201/09436 ,  H05K2201/09563 ,  H05K3/4076 ,  H05K3/4644 ,  Y10T29/49156

Abstract: A multilayer wiring substrate is disclosed which includes a reconfigurable link structure for effecting wiring change. A plurality of pad portions are connected to a link structure through holes on an insulating layer located therebetween which also acts as a solder dam. A gap is present on a portion of the insulating layer through which a portion of the link structure is exposed. By cutting away the portion so exposed, the link structure is divided, and pad portions connected to the divided portions of the link structure become disconnected. An external wire may be selectively soldered to any one pad portion while the insulating layer acts as a soldering dam for preventing flow of solder onto the base wiring substrate section below the link structure. Because the insulating layer acts as a solder dam, the pad portions may be fabricated with materials conducive to solder wettability and severability.

Abstract translation: 公开了一种多层布线基板，其包括用于实现布线改变的可重构链路结构。 多个焊盘部分通过位于其间的绝缘层上的孔连接到连接结构，其也用作焊接坝。 在绝缘层的一部分存在间隙，通过该部分露出连接结构的一部分。 通过切除暴露的部分，链接结构被分割，并且连接到链接结构的分割部分的焊盘部分断开。 外部导线可以选择性地焊接到任何一个焊盘部分，同时绝缘层用作防止焊料流向连接结构下方的基底布线基板部分上的焊接坝。 由于绝缘层用作焊料坝，焊盘部分可以用有助于焊料润湿性和可分割性的材料制成。

公开(公告)号：US3648364A

公开(公告)日：1972-03-14

申请号：US3648364D

申请日：1970-04-30

Applicant: HOKURIKU ELECT IND

Inventor： ENDO TSUNEHIKO

IPC: H01C1/14 ,  H01C7/00 ,  H05K1/09 ,  H05K1/16 ,  H05K3/06 ,  H05K3/28 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01C17/00

CPC classification number: H05K1/167 ,  H01C1/14 ,  H01C7/00 ,  H05K1/095 ,  H05K3/06 ,  H05K3/28 ,  H05K3/386 ,  H05K3/42 ,  H05K3/427 ,  H05K3/4664 ,  H05K2201/0323 ,  H05K2201/035 ,  H05K2201/09436 ,  H05K2201/09881 ,  H05K2203/1453 ,  Y10T29/49099 ,  Y10T29/49101 ,  Y10T29/4913

Abstract: A printed resistor comprising an insulating matrix board, copper layers printed on one side of said board by etching and having predetermined patterns, impedance layers screen printed on the other side of said board, and conductors applied in holes formed in said board and extending through said holes for electrically connecting between selected ones of said copper layers and said impedance layers and the process for producing said printed resistor.

Abstract translation: 一种印刷电阻器，包括绝缘矩阵板，通过蚀刻印刷在所述板的一侧上并具有预定图案的铜层，印刷在所述板的另一侧上的阻挡层丝网印刷，以及施加在形成在所述板中并延伸穿过所述板的孔中的导体 用于电连接所述铜层中的所选铜层和所述阻抗层的孔以及用于制造所述印刷电阻器的工艺。

公开(公告)号：US3629185A

公开(公告)日：1971-12-21

申请号：US3629185D

申请日：1969-10-17

Applicant: KOLLMORGEN CORP

Inventor： SCHNEBLE FREDERICK W JR ,  LEECH EDWARD JOHN ,  MCCORMACK JOHN FRANCIS

IPC: B01J31/08 ,  B01J31/30 ,  B01J47/00 ,  C08K3/00 ,  C23C18/16 ,  C23C18/20 ,  C23C18/28 ,  H05K1/03 ,  H05K3/28 ,  H05K3/42 ,  C08G51/04

CPC classification number: B01J31/30 ,  B01J31/08 ,  B01J47/016 ,  C08K3/013 ,  C23C18/1608 ,  H05K1/0373 ,  H05K3/28 ,  H05K3/422 ,  H05K2201/0209 ,  H05K2201/0236 ,  H05K2201/09436 ,  C08L67/06

Abstract: THERE ARE PROVIDED MOLDING COMPOSITIONS COMPRISING PARTICLES OF RESIN HAVING INCORPORATED THEREWITH FILLERS CATALYTIC TO THE DEPOSITION OF ELECTROLESS METALS. THE CATALYTIC FILLERS ARE MADE BY REPLACING THE CATIONS IN PARTICULATE BASE EXCHANGEABLE MATERIALS WITH A CATION OF A METAL SELECTED FROM GROUPS 1 B AND 8 OF THE PERIODIC TABLE OF ELEMENTS. ARTICLES MOLDED FROM THE COMPOSITIONS AND THE WALLS OF HOLES DRILLED IN THEM ARE METALLIZED ON BEING IMMERSED IN ELECTROLESS METAL DEPOSITION BATHS.

公开(公告)号：US11646290B2

公开(公告)日：2023-05-09

申请号：US17340350

申请日：2021-06-07

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Jong Ok Chun ,  Nozad Karim ,  Richard Chen ,  Giuseppe Selli ,  Michael Kelly

IPC: H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/552 ,  H05K1/02 ,  H05K7/10 ,  H01L23/31 ,  H05K1/11 ,  H05K1/16

CPC classification number: H01L24/49 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/552 ,  H01L23/66 ,  H05K1/0215 ,  H05K7/10 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/115 ,  H05K1/165 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/10287 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

公开(公告)号：US20170374747A1

公开(公告)日：2017-12-28

申请号：US15622733

申请日：2017-06-14

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K3/40 ,  H01L23/00 ,  H05K3/46 ,  H05K1/11 ,  H05K3/26 ,  H05K3/10 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K3/4007 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81805 ,  H01L2924/00011 ,  H01L2924/01322 ,  H05K1/112 ,  H05K3/0041 ,  H05K3/108 ,  H05K3/26 ,  H05K3/3473 ,  H05K3/4647 ,  H05K2201/09436 ,  H05K2201/10674 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/043 ,  H05K2203/0465 ,  H01L2924/00014

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

公开(公告)号：US09661750B2

公开(公告)日：2017-05-23

申请号：US14364013

申请日：2012-11-30

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Kyoung Jo ,  Seol Hee Lim ,  Chang Hwa Park ,  Sai Ran Eom ,  Ae Rim Kim

IPC: H05K1/09 ,  H05K3/18 ,  H05K3/24

CPC classification number: H05K1/092 ,  H05K3/182 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0341 ,  H05K2201/09436 ,  H05K2201/099 ,  Y10T29/49155

Abstract: Provided is a printed circuit board, including: a circuit pattern or a base pattern formed on an insulating layer; and a plurality of metal layers formed on the circuit pattern or the base pattern, wherein the metal layers includes: a silver metal layer formed of a metal material including silver; a first palladium metal layer formed at a lower part of the silver metal layer; and a second palladium metal layer formed at an upper part of the silver metal layer.

公开(公告)号：US09443788B2

公开(公告)日：2016-09-13

申请号：US13966633

申请日：2013-08-14

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H05K1/11 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H05K3/42 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/05647 ,  H01L2924/01024 ,  H01L2924/01079

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

Abstract translation: 一种制造通孔电极基板的方法包括在基板上形成多个通孔，通过在多个通孔中填充导电材料形成多个通孔电极，在一个通孔上形成第一绝缘层 在所述第一绝缘层上形成多个第一开口，所述多个第一开口将与所述多个通孔电极中的每一个相对应的多个通孔电极暴露在所述第一绝缘层上，并且使用所述关系来校正所述多个第一开口的位置 在多个通孔中的倾斜通孔的打开位置的测量距离值的偏移量与多个通孔中的倾斜通孔的打开位置的设计距离值之间， 相对于基板的中心位置。

公开(公告)号：US09433117B1

公开(公告)日：2016-08-30

申请号：US13475469

申请日：2012-05-18

Applicant: Jong Ok Chun ,  Nozad Karim ,  Richard Chen ,  Giuseppe Selli ,  Michael Kelly

Inventor： Jong Ok Chun ,  Nozad Karim ,  Richard Chen ,  Giuseppe Selli ,  Michael Kelly

IPC: H05K7/10 ,  H05K1/02

CPC classification number: H01L24/49 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/115 ,  H05K1/165 ,  H05K7/10 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/10287 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

Abstract translation: 电子部件封装包括基板和安装到基板的电子部件，电子部件包括接合焊盘。 第一天线端子电连接到接合焊盘，第一天线端子电连接到衬底的第二天线端子。 封装体包围电子部件，封装主体具有主表面。 通过施加导电涂层在主表面上形成天线。 嵌入式互连件在基板和主表面之间延伸穿过封装主体并将第二天线端子电连接到天线。 施加导电涂层以形成天线相对简单，从而使整体封装制造成本最小化。 此外，天线相对较薄，从而使整体封装尺寸最小化。

公开(公告)号：US09392695B2

公开(公告)日：2016-07-12

申请号：US14321068

申请日：2014-07-01

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Min Gi Cho

IPC: H05K1/16 ,  H05K7/00 ,  H05K1/18 ,  H05K1/14 ,  H05K3/28 ,  H01L23/498 ,  H01L21/56 ,  H01L23/13 ,  H05K1/02 ,  H05K1/11 ,  H01L23/31 ,  H01L23/50

CPC classification number: H05K1/181 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/1531 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K3/28 ,  H05K2201/09436 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10378 ,  H05K2201/2018 ,  H05K2203/1327

Abstract: There is provided an electronic component module capable of increasing the degree of integration by mounting electronic components on both surfaces of a substrate. The electronic component module according to an exemplary embodiment of the present disclosure includes a first substrate having one surface on which at least one electronic component is mounted; and a second substrate bonded to one surface of the first substrate and including at least one component accommodating part in which the at least one electronic component is accommodated, wherein the second substrate includes a core layer, and metal wiring layers formed on both surfaces of the core layer and having a plurality of electrode pads.

Abstract translation: 提供了一种能够通过将电子部件安装在基板的两个表面上而增加集成度的电子部件模块。 根据本公开的示例性实施例的电子部件模块包括具有一个表面的第一基板，至少一个电子元件安装在该表面上; 以及第二基板，其接合到所述第一基板的一个表面并且包括容纳所述至少一个电子部件的至少一个部件容纳部，其中所述第二基板包括芯层，以及形成在所述第二基板的两个表面上的金属布线层 并具有多个电极焊盘。

公开(公告)号：US20150195912A1

公开(公告)日：2015-07-09

申请号：US14150683

申请日：2014-01-08

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/03 ,  H05K3/46

CPC classification number: H05K3/4007 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81805 ,  H01L2924/00011 ,  H01L2924/01322 ,  H05K1/112 ,  H05K3/0041 ,  H05K3/108 ,  H05K3/26 ,  H05K3/3473 ,  H05K3/4647 ,  H05K2201/09436 ,  H05K2201/10674 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/043 ,  H05K2203/0465 ,  H01L2924/00014

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract translation: 一种将芯片附着到具有外层的方法，外层包括嵌入电介质如焊料掩模中的通孔，通孔的端部与所述电介质齐平，所述方法包括以下步骤：（o）任选地除去有机清漆 ，（p）将具有用焊料凸块端接的腿的芯片定位成与通孔柱的暴露端接触，和（q）施加热量以熔化焊料凸块并用焊料润湿通孔的端部。