公开(公告)号：USRE44251E1

公开(公告)日：2013-06-04

申请号：US10839813

申请日：2004-05-06

Applicant: Motoo Asai ,  Yoichiro Kawamura ,  Yoji Mori

Inventor： Motoo Asai ,  Yoichiro Kawamura ,  Yoji Mori

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

公开(公告)号：US08450621B2

公开(公告)日：2013-05-28

申请号：US12328446

申请日：2008-12-04

Applicant: Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

Inventor： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/14 ,  H05K7/00 ,  H05K1/18

CPC classification number: H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

公开(公告)号：US20130107482A1

公开(公告)日：2013-05-02

申请号：US13665325

申请日：2012-10-31

Applicant: Yasushi INAGAKI ,  Motoo ASAI ,  Dongdong WANG ,  Hideo YABASHI ,  Seiji SHIRAI

Inventor： Yasushi INAGAKI ,  Motoo ASAI ,  Dongdong WANG ,  Hideo YABASHI ,  Seiji SHIRAI

IPC: H05K1/18

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract translation: 印刷电路板包括容纳层，容纳层中容纳的片状电容器器件，以及形成在容纳层上的堆积结构，使得堆积结构覆盖容纳层中的片状电容器器件。 积层结构具有安装导体结构，其被定位成将IC芯片装置安装在积层结构的表面上，使得IC芯片装置直接安装在芯片电容器装置上，每个芯片电容器装置具有电介质体， 所述积聚结构，形成在所述电介质体上且在所述电介质体的表面上延伸的第一电极，以及形成在所述电介质体上并在所述电介质体的表面上延伸的第二电极，并且所述电介质体介于所述第一电极 电极和第二电极。

公开(公告)号：US08377506B2

公开(公告)日：2013-02-19

申请号：US12574350

申请日：2009-10-06

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: B05D5/12 ,  C25D5/02 ,  C23C14/00

CPC classification number: H05K3/4007 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/112 ,  H05K3/243 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract translation: 提供了基板结构。 基板结构包括基板，第一绝缘层，导电部件，第二绝缘层，种子层和导电层。 衬底具有分别位于衬底的两个相对表面上的第一电路图案层和第二电路图案层。 形成在第一电路图案层上的第一绝缘层具有第一绝缘孔，其暴露第一绝缘层的外表面中的第一开口。 形成在与芯片电连接的第一绝缘孔上的导电部分被第一开口的边缘包围。 形成在第二电路图案层上的第二绝缘层具有形成种子层的第二绝缘孔。 导电层形成在种子层上，用于与电路板电连接。

公开(公告)号：US08349727B2

公开(公告)日：2013-01-08

申请号：US13083111

申请日：2011-04-08

Applicant: Liang Guo ,  Stephen P. DeWeerth

Inventor： Liang Guo ,  Stephen P. DeWeerth

IPC: H01L21/4763

CPC classification number: H05K3/4644 ,  A61N1/0543 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K1/0283 ,  H05K1/185 ,  H05K3/4691 ,  H05K2201/09509 ,  H01L2924/00

Abstract: Stretchable multi-chip modules (SMCMs) are capable of withstanding large mechanical deformations and conforming to curved surfaces. These SMCMs may find their utilities in elastic consumer electronics such as elastic displays, skin-like electronic sensors, etc. In particular, stretchable neural implants provide improved performances as to cause less mechanical stress and thus fewer traumas to surrounding soft tissues. Such SMCMs usually comprise of various electronic components attached to or embedded in a polydimethylsiloxane (PDMS) substrate and wired through stretchable interconnects. However, reliably and compactly connecting the electronic components to PDMS-based stretchable interconnects is very challenging. This invention describes an integrated method for high-density interconnection of electronic components through stretchable interconnects in an SMCM. This invention has applications in high-density SMCMs, as well as high-density stretchable/conformable neural interfaces.

Abstract translation: 可伸缩的多芯片模块（SMCM）能够承受大的机械变形并符合曲面。 这些SMCM可以在诸如弹性显示器，皮肤样电子传感器等的弹性消费电子产品中发现它们的用途。特别地，可拉伸的神经植入物提供改善的性能，从而导致较少的机械应力，从而减少周围软组织的创伤。 这样的SMCM通常包括连接到或嵌入在聚二甲基硅氧烷（PDMS）衬底中并通过可拉伸互连线布线的各种电子部件。 然而，将电子元件可靠且紧凑地连接到基于PDMS的可拉伸互连是非常具有挑战性的。 本发明描述了一种用于通过SMCM中的可伸缩互连实现电子部件的高密度互连的集成方法。 本发明可应用于高密度SMCM，以及高密度可伸缩/神经接口。

公开(公告)号：US08345433B2

公开(公告)日：2013-01-01

申请号：US11177508

申请日：2005-07-08

Applicant: George E. White ,  Sidharth Dalmia ,  Venkatesh Sundaram ,  Madhavan Swaminathan

Inventor： George E. White ,  Sidharth Dalmia ,  Venkatesh Sundaram ,  Madhavan Swaminathan

IPC: H05K1/18

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L23/055 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/183 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/061 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Organic laminate stack ups are disclosed for a variety of applications, including high frequency RF applications. One or more inner core layers may be disposed between outer layers along with bondply or prepreg layers as needed. Discrete devices, including surface mount components and flip chips, may be embedded within the organic laminate stack up structures. The embedding of the discrete devices, which may be active or passive devices, may be in the form of a layer of bondply or prepreg encapsulating the discrete devices. In addition or in the alternative, cavities may be formed in at least the outer layers for housing discrete devices, which include surface mount components, flip chips, and wire bonded integrated circuits. A variety of caps may be utilized to seal the cavities. Further, shielding may be provided for the organic laminate stack up structure, including through a wall of vias or a plated trench cut along at least one side of the stack up structure. Each stack up structure may be packaged in a variety of ways, including as a surface mount component, ball grid array, or land grid array.

Abstract translation: 公开了有机层压叠层用于各种应用，包括高频RF应用。 根据需要，一个或多个内芯层可以与键合层或预浸料层一起设置在外层之间。 分立器件，包括表面贴装元件和倒装芯片，可嵌入有机叠层堆叠结构内。 可以是有源或无源器件的分立器件的嵌入可以是封装分立器件的键合层或预浸料的形式。 另外或在替代方案中，空腔可以形成在至少外层中，用于容纳包括表面安装部件，倒装芯片和引线键合集成电路的分立器件。 可以使用各种盖来密封空腔。 此外，可以提供用于有机层叠叠层结构的屏蔽，包括穿过通孔壁或沿堆叠结构的至少一侧切割的电镀沟槽。 每个堆叠结构可以以各种方式包装，包括作为表面安装部件，球栅阵列或平台网格阵列。

公开(公告)号：US08336205B2

公开(公告)日：2012-12-25

申请号：US13209052

申请日：2011-08-12

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/188 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层，第二绝缘层和导电膜的基底基板的方法制造印刷线路板。 在基于对准标记确定的位置处将电子部件放置在第一绝缘层上。 在将电子部件封闭在第二绝缘层的开口内之后，在基于对准标记确定的位置处形成暴露电子部件的端子的通孔，该位置用于确定电子部件的位置。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US08323771B1

公开(公告)日：2012-12-04

申请号：US11839277

申请日：2007-08-15

Applicant: Ronald Patrick Huemoeller ,  Sukianto Rusli

Inventor： Ronald Patrick Huemoeller ,  Sukianto Rusli

IPC: B32B3/24 ,  H05K1/11

CPC classification number: H05K1/116 ,  H01L2224/73204 ,  H05K1/0269 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/4007 ,  H05K3/428 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2201/2072 ,  Y10T428/24331 ,  Y10T428/24917

Abstract: A capture pad structure includes a first dielectric layer. A trace is embedded within the first dielectric layer. A capture pad is also embedded within the first dielectric layer, the capture pad being an end portion of the trace. A blind via aperture extends partially through the first dielectric layer from a principal surface of the first dielectric layer to the capture pad. By forming the capture pad as the end portion of the trace, formation of the capture pad requires no change in direction or complex motion of the laser.

Abstract translation: 捕获垫结构包括第一介电层。 迹线嵌入在第一介电层内。 捕获垫也嵌入在第一介电层内，捕获垫是痕迹的端部。 盲通孔从第一电介质层的主表面部分延伸穿过第一介电层到捕获垫。 通过将捕获垫形成为迹线的端部，捕获垫的形成不需要激光的方向或复杂运动的变化。

公开(公告)号：US20120302010A1

公开(公告)日：2012-11-29

申请号：US13561247

申请日：2012-07-30

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H01L21/58

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract translation: 一种制造印刷电路板的方法包括在第一金属层上形成含有原料陶瓷材料的未煅烧层，焙烧形成在第一金属层上的未煅烧层，使得具有以片状形式煅烧的陶瓷体的高介电常数层 形成在第一金属层上，相对于第一金属层在高介电常数层的相对侧的高介电常数层上形成第二金属层，使得具有高介电常数层的层状电容器和第一金属层 形成夹着高介电常数层的第二层电极，并将层叠电容器配置在主体中。

公开(公告)号：US08299369B2

公开(公告)日：2012-10-30

申请号：US12605198

申请日：2009-10-23

Applicant: Gary A. Brist ,  Gary Baxter Long ,  Daryl A. Sato

Inventor： Gary A. Brist ,  Gary Baxter Long ,  Daryl A. Sato

IPC: H05K1/11

CPC classification number: H05K1/0265 ,  H05K1/0206 ,  H05K1/0219 ,  H05K1/0221 ,  H05K3/005 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Abstract translation: 一种包括多个金属化平面的装置，一个或多个分离多个金属化平面的电介质层; 以及连接到所述多个金属化平面中的至少一个的一个或多个导电沟槽。