公开(公告)号：US20110249416A1

公开(公告)日：2011-10-13

申请号：US13079940

申请日：2011-04-05

Applicant: Kiyofumi TAKAI

Inventor： Kiyofumi TAKAI

IPC: H05K7/00 ,  H05K3/30

CPC classification number: H05K3/284 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/023 ,  H05K3/0052 ,  H05K2201/0715 ,  H05K2201/10204 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a circuit module, a chip element is mounted on a mount electrode, with an outer electrode interposed therebetween. The chip element is arranged such that a cut surface thereof is oriented toward a side of a circuit module that is adjacent to the mount electrode. A gap that is observable from outside of the circuit module is provided between a bottom surface of a base of the chip element and a top surface of a circuit board.

Abstract translation: 在电路模块中，芯片元件安装在安装电极上，其中插入有外部电极。 芯片元件布置成使得其切割表面朝向邻近安装电极的电路模块的侧面。 从电路模块外部观察到的间隙设置在芯片元件的基座的底表面和电路板的顶表面之间。

公开(公告)号：US20110140731A1

公开(公告)日：2011-06-16

申请号：US12958869

申请日：2010-12-02

Applicant: Swen Weitemeier ,  Christian Oldendorf

Inventor： Swen Weitemeier ,  Christian Oldendorf

IPC: G01R31/28

CPC classification number: G01R31/2815 ,  G01R31/2839 ,  G06F21/86 ,  H05K1/0275 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: An electronic device, and associated method, provided with a circuit board (10) with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM), and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least one inductive element, which is formed by a conductor wire (201) wound into a coil around a break (202) in the circuit board (10), which in the assembled condition, is penetrated by a ferromagnetic bar or fixing pin (203), such that the inductance of the inductive element in the assembled state differs from the inductance thereof in the disassembled state.

Abstract translation: 一种具有电路板（10）的电子设备和相关方法，所述电路板具有一组输入触点（IN / COM），一组输出触点（OUT / COM）和连接在输入触点之间的电路（18） （IN / COM）和输出触点（OUT / COM）和控制器。 控制器使用引入到电路中的测试信号来执行电路板的实时测试，电路（18）被设计为具有特征传递函数并具有至少一个电感元件的无源网络，其中 由绕在电路板（10）中的断路（202）周围卷绕成线圈的导体线（201）形成，在组装状态下，该导体线被铁磁棒或固定销（203）穿透，使得电感 在组装状态下的电感元件与其分解状态下的电感不同。

公开(公告)号：US07944711B2

公开(公告)日：2011-05-17

申请号：US12396108

申请日：2009-03-02

Applicant: Elio Marioni

Inventor： Elio Marioni

IPC: H05K7/02

CPC classification number: H05K1/0209 ,  H05K1/145 ,  H05K3/3426 ,  H05K3/3447 ,  H05K2201/09781 ,  H05K2201/10166 ,  H05K2201/10204 ,  H05K2201/10522 ,  H05K2201/1056 ,  H05K2201/10757 ,  Y10T29/4913

Abstract: The present invention relates to a substantially package-like discrete electronic component of the type comprising a power electronic circuit, a body or casing, substantially parallelepiped, and electric connecting pins connected inside the body with said circuit and projecting from said body for an electric connection on the electronic printed circuit board. The body has a heat dissipating header having at least one surface emerging from the body and laying on a plane whereas the pins project from the body for a first section initially extended parallel to the plane. Advantageously a pair of pins has a substantially U-shaped bending, after the first section parallel to the plane for allowing a more stable bearing of the component during the step of welding to a heat dissipating intermediate die.

Abstract translation: 本发明涉及一种基本上包装状的分立电子部件，其类型包括主电源电路，主体或壳体，基本上平行六面体的电连接销和连接在主体内的所述电路的电连接销，并从所述主体突出以进行电连接 在电子印刷电路板上。 主体具有散热头部，其具有至少一个从主体出来并放置在平面上的表面，而销从主体突出出来，第一部分最初平行于平面延伸。 有利的是，在第一部分平行于平面之后，一对销具有基本上U形的弯曲，以便在焊接到散热中间管芯的步骤期间允许部件的更稳定的轴承。

公开(公告)号：US20100207651A1

公开(公告)日：2010-08-19

申请号：US12707930

申请日：2010-02-18

Applicant: Anthony J. Suto

Inventor： Anthony J. Suto

IPC: G01R31/02

CPC classification number: G01R31/2818 ,  H05K1/0268 ,  H05K3/3442 ,  H05K2201/10022 ,  H05K2201/10204 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A reliable and durable method of testing of printed circuit boards is presented. Test access components are placed in contact regions for providing electrical connectivity between test probes and the printed circuit board. In some cases, a test access component may be a surface mount resistor. The test access component may provide two points of contact for test probes to make electrical and mechanical contact with the printed circuit board. Test access components may also provide for increased durability of testing, allowing for a greater number of test contacts to be made between test probes and printed circuit boards than were previously possible.

Abstract translation: 介绍了一种可靠耐用的印刷电路板测试方法。 测试访问组件放置在接触区域中，以提供测试探针与印刷电路板之间的电连接。 在某些情况下，测试访问组件可能是表面贴装电阻。 测试访问组件可以为测试探针提供两个接触点，以与印刷电路板进行电气和机械接触。 测试访问组件还可以提供更高的测试耐久性，允许在测试探针和印刷电路板之间进行比以前更多的测试接触。

公开(公告)号：US20090180263A1

公开(公告)日：2009-07-16

申请号：US12008836

申请日：2008-01-14

Applicant: Christopher Lee Eriksen ,  Howard David Goldberg ,  John Charles Meyer

Inventor： Christopher Lee Eriksen ,  Howard David Goldberg ,  John Charles Meyer

IPC: H05K5/00 ,  H05K7/00 ,  B23P11/00

CPC classification number: H05K1/147 ,  H05K1/0256 ,  H05K2201/10204 ,  H05K2201/2036 ,  Y10T29/49826

Abstract: A compliant circuit element spacing system comprises a circuit board, a dummy spacer component, and a compliant circuit element. One or more active components are mounted to the circuit board. The dummy spacer component is also mounted to the circuit board, such that the dummy spacer component is electrically isolated from each active component mounted to the circuit board. The compliant circuit element is positionable proximate the circuit board, and spaced from the circuit board by the dummy spacer component. The spacing component isolates the compliant circuit element from each active component mounted to the circuit board.

Abstract translation: 兼容电路元件间隔系统包括电路板，虚拟间隔件部件和兼容电路元件。 一个或多个有源部件被安装到电路板。 虚拟间隔器部件也安装到电路板，使得虚拟间隔件部件与安装到电路板的每个有源部件电隔离。 柔性电路元件可靠近电路板定位，并且通过虚拟间隔器部件与电路板间隔开。 间隔部件将兼容电路元件与安装到电路板的每个有源部件隔离。

公开(公告)号：US20070194446A1

公开(公告)日：2007-08-23

申请号：US11657387

申请日：2007-01-24

Applicant: Hermann Ruckerbauer

Inventor： Hermann Ruckerbauer

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/14 ,  G11C5/04 ,  H01L2924/15311 ,  H05K1/0295 ,  H05K1/117 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10204

Abstract: A memory module is proposed which has a first contact bank at a first edge of its electronic printed circuit board and a second contact bank at a second edge. The printed circuit board has first lines that reach from the first contact bank as far as input connections of at least some of the semiconductor components. The printed circuit board has second conductor lines that reach from output connections of at least some of the semiconductor components as far as the first contact bank. The printed circuit board has third conductor lines that reach from output connections of at least some of the semiconductor components as far as the second contact bank. The printed circuit board has fourth conductor lines that reach from the second contact bank as far as input connections of at least some of the semiconductor components.

Abstract translation: 提出一种存储器模块，其在其电子印刷电路板的第一边缘处具有第一触点组，在第二边缘处具有第二触点组。 印刷电路板具有从第一触点组到达至少一些半导体部件的输入连接的第一线。 印刷电路板具有从至少一些半导体部件的输出连接到达第一触点组的第二导体线。 印刷电路板具有从至少一些半导体部件的输出连接到达第二触点组的第三导体线。 印刷电路板具有从第二触点组到达至少一些半导体部件的输入连接的第四导体线。

公开(公告)号：US20060288567A1

公开(公告)日：2006-12-28

申请号：US11468231

申请日：2006-08-29

Applicant: Shawn Lloyd ,  John Oldendorf ,  Michael Kochanowski ,  Scott Gilbert

Inventor： Shawn Lloyd ,  John Oldendorf ,  Michael Kochanowski ,  Scott Gilbert

IPC: H01H11/00 ,  H05K3/30 ,  H05K3/00

CPC classification number: H01L23/62 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10181 ,  H05K2201/10204 ,  H05K2201/2036 ,  H05K2203/1572 ,  Y10T29/49105 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.

Abstract translation: 一种器件包括衬底。 衬底还包括包括多个焊盘的第一主表面和第二主表面。 至少一个部件附接到第一主表面上的多个焊盘中的至少一些。 至少一个牺牲部件附接到第一主表面。 所述至少一个部件相对于所述第一主表面具有第一高度，并且所述至少一个牺牲部件相对于所述第一主表面具有第二高度。 第二个高度大于第一个高度。 牺牲部件包括保险丝。

公开(公告)号：US07094975B2

公开(公告)日：2006-08-22

申请号：US10717839

申请日：2003-11-20

Applicant: Suresh K. Chengalva ,  David W. Ihms ,  Bruce A. Myers

Inventor： Suresh K. Chengalva ,  David W. Ihms ,  Bruce A. Myers

IPC: H05K1/03

CPC classification number: H05K1/0206 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/0271 ,  H05K3/0061 ,  H05K2201/068 ,  H05K2201/10204 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: A circuit board assembly comprising a laminate substrate and a surface mount device having a CTE less than that of the laminate substrate and attached with at least one solder joint to a first surface of the laminate substrate. The assembly further includes a localized stiffener attached to a second surface of the laminate substrate so as to be directly opposite the circuit device. The localized stiffener is formed of a material and is shaped so that, when attached to the laminate substrate, the stiffener is capable of increasing the thermal cycle fatigue life of the one or more solder joints that attach the device to the substrate.

Abstract translation: 一种电路板组件，包括层压基板和表面安装装置，所述表面安装装置的CTE小于层压基板的CTE，并且与至少一个焊接接头连接到层叠基板的第一表面。 组件还包括附着到层叠基板的第二表面以便与电路装置直接相对的局部加强件。 局部加强件由材料形成并且被成形为使得当附接到层叠基板时，加强件能够增加将该装置附接到基板的一个或多个焊点的热循环疲劳寿命。

公开(公告)号：US07015823B1

公开(公告)日：2006-03-21

申请号：US10966593

申请日：2004-10-15

Applicant: Robert Joseph Gillen ,  Todd Scott Grimes

Inventor： Robert Joseph Gillen ,  Todd Scott Grimes

IPC: G08B21/00 ,  G08B13/00

CPC classification number: G08B13/128 ,  G08B21/0213 ,  H05K1/0275 ,  H05K1/0286 ,  H05K3/284 ,  H05K2201/10151 ,  H05K2201/10204 ,  H05K2201/10212

Abstract: A physical barrier for a circuit board also functions as a tampering sensor or sensors monitored by electrical circuitry that generates a tamper signal for erasing information critical for the operation of the circuit board in the event of sensed tampering. One or more routing matrices configured in at least one programmable device is programmed to interconnect operating as well as optional dummy components on the board so that routing information is erased in the event of sensed tampering.

Abstract translation: 用于电路板的物理屏障还用作由电路监控的篡改传感器或传感器，该传感器或传感器产生篡改信号，以在发生篡改的情况下擦除对电路板操作至关重要的信息。 配置在至少一个可编程设备中的一个或多个路由矩阵被编程为在板上互连操作以及可选的虚拟部件，使得在感测到的篡改的情况下擦除路由信息。

公开(公告)号：US06995321B2

公开(公告)日：2006-02-07

申请号：US10039942

申请日：2002-01-03

Applicant: Bruce W. Lee ,  Jesse L. Pedigo

Inventor： Bruce W. Lee ,  Jesse L. Pedigo

IPC: H05K1/00

CPC classification number: H05K3/1233 ,  H05K3/0094 ,  H05K3/4053 ,  H05K3/4069 ,  H05K2201/0959 ,  H05K2201/10204 ,  H05K2203/0126 ,  H05K2203/0139 ,  H05K2203/0156 ,  H05K2203/0182 ,  H05K2203/0554 ,  H05K2203/1105

Abstract: An assembly is disclosed that includes an etched hole-fill standoff; a tooling plate contacting the etched hole-fill stand-off, the stand-off and tooling plate being aligned to each other; a device having holes to be filled removably contacting the stand-off, the stand-off and device being aligned to each other; the device and the stand-off each having at least one hole, the hole of the device being aligned with the hole of the stand-off. An assembly is also disclosed comprising an etched hole-fill standoff, the stand-off comprising an etched layer bonded to a non-etched layer. A method of filling holes in a substrate having a plurality of holes to be filled includes the steps of providing an etched hole-fill stand-off, aligning the stand-off to a tooling plate, aligning the substrate to the stand off and placing the substrate in contact with the stand-off, and filling the plurality of holes of the substrate.