公开(公告)号：US20030156232A1

公开(公告)日：2003-08-21

申请号：US10366409

申请日：2003-02-14

Inventor： Masuyuki Ohta ,  Masahiro Ishi ,  Kikuo Ono ,  Nobuyuki Suzuki

IPC: G02F001/136

CPC classification number: G02F1/134363 ,  G02F1/133345 ,  G02F1/1368 ,  G02F2001/136218 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/10136 ,  H05K2201/10681

Abstract: An active matrix type liquid crystal display device includes a first and second substrate with a liquid crystal layer therebetween, a plurality of drain lines and gate lines formed on the first substrate and crossing each other in a matrix form, a plurality of pixels formed by adjoining the drain lines and the gate lines, at least a counter electrode and at least a pixel electrode formed on the first substrate in each pixel; and at least a light blocking film formed on one of the first and second substrate. The light blocking film is arranged substantially parallel to the gate line and each light blocking film is spaced from and in overlapping relation with the drain line. At least one counter electrode has an overlapping relation with the drain line in plan view and extends in a region of the light blocking film. The counter electrode is made of a transparent conductive layer, and the liquid crystal display device has a normally black mode.

Abstract translation: 有源矩阵型液晶显示装置包括：第一和第二基板，其间具有液晶层，多个排列线和栅极线，形成在第一基板上并以矩阵形式彼此交叉;多个像素，邻接形成 漏极线和栅极线，至少在每个像素中形成在第一衬底上的对电极和至少一个像素电极; 并且至少形成在所述第一和第二基板中的一个上的遮光膜。 遮光膜基本上平行于栅极线布置，并且每个遮光膜与漏极线隔开并且与漏极线重叠。 至少一个对电极在平面图中与排泄线具有重叠关系，并且在遮光膜的区域中延伸。 对电极由透明导电层制成，液晶显示装置具有常黑模式。

公开(公告)号：US20030065367A1

公开(公告)日：2003-04-03

申请号：US09970145

申请日：2001-10-02

Inventor： Nick A. Youker ,  Ronald L. Anderson ,  John E. Hansen

IPC: A61N001/375

CPC classification number: H05K1/189 ,  A61N1/375 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/113 ,  H05K3/4069 ,  H05K2201/10545 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.

Abstract translation: 一种胶带自动接合（TAB）结构，其包括在其上形成导电图案的柔性带。 导电引线图形包括多个引线，其被配置为形成TAB结构的内部引线键合（ILB）部分。 所述多个引线中的至少一个在内部布线并且具有暴露在TAB结构的ILB部分内部的触点。

公开(公告)号：US06528870B2

公开(公告)日：2003-03-04

申请号：US09769394

申请日：2001-01-26

Applicant: Kenta Fukatsu ,  Yasuhito Saito ,  Masayuki Arakawa ,  Tomohiro Iguchi ,  Naotake Watanabe ,  Yoshitoshi Fukuchi ,  Tetsuro Komatsu

Inventor： Kenta Fukatsu ,  Yasuhito Saito ,  Masayuki Arakawa ,  Tomohiro Iguchi ,  Naotake Watanabe ,  Yoshitoshi Fukuchi ,  Tetsuro Komatsu

IPC: H01L2302

CPC classification number: H05K3/363 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/144 ,  H05K3/3442 ,  H05K2201/0394 ,  H05K2201/09181 ,  H05K2201/096 ,  H05K2201/0969 ,  H05K2201/10681

Abstract: In a stacked-type semiconductor unit having a plurality of semiconductor devices stacked on a base board including a base electrode, each semiconductor device has a wiring board including an external electrode provided in an end portion thereof. The semiconductor devices are stacked on the base board such that the external electrodes are aligned with one another. Then, the external electrodes are electrically connected to the base board by solder.

Abstract translation: 在具有堆叠在包括基极的基板上的多个半导体器件的叠层型半导体单元中，每个半导体器件具有包括设置在其端部中的外部电极的布线板。 半导体器件堆叠在基板上，使得外部电极彼此对准。 然后，外部电极通过焊料与基板电连接。

公开(公告)号：US20030022558A1

公开(公告)日：2003-01-30

申请号：US10201777

申请日：2002-07-25

Applicant: SEIKO EPSON CORPORATION

Inventor： Norio Imaoka

IPC: H01R024/00

CPC classification number: H01R12/62 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H01R12/7076 ,  H01R31/06 ,  H05K1/111 ,  H05K1/117 ,  H05K3/361 ,  H05K2201/09418 ,  H05K2201/10681 ,  H01L2924/00

Abstract: An electronic device includes first and second electronic components. Each of terminals of a first group of the first electronic component is disposed on one of a plurality of first lines passing through a first point. Each of terminals of a second group of the second electronic component is disposed on one of a plurality of second lines passing through a second point. The first and second points coincide with each other, and the first and second lines overlap. The terminals of at least one of the first and second groups are formed to extend along first lines or second lines.

Abstract translation: 电子设备包括第一和第二电子部件。 第一组电子部件的第一组的端子设置在通过第一点的多条第一线之一上。 第二组电子部件的第二组的每个端子设置在通过第二点的多条第二线中的一条上。 第一和第二点彼此重合，第一和第二行重叠。 第一组和第二组中的至少一个的端子形成为沿着第一线或第二线延伸。

公开(公告)号：US20030006489A1

公开(公告)日：2003-01-09

申请号：US09900333

申请日：2001-07-06

Inventor： Kenzo Fujii ,  Taro Hirai

IPC: H01L023/495 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L23/4985 ,  H01L21/4846 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K1/0393 ,  H05K3/062 ,  H05K3/108 ,  H05K3/181 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A flexible wiring substrate for coupling between a semiconductor element and a circuit substrate. The flexible wiring substrate comprises a base material layer made of insulating and flexible material, and wiring conductors formed on the base material layer. The wiring conductors are formed of at least one electroless plated layer and at least one electroplated layer formed on the at least one electroless plated layer. The wiring conductors are formed apart from a peripheral edge portion of the base material layer. A power supply line for electroplating used for forming the electroplated layer does not remain on the base material layer. The wiring conductors have, for example, a multi-layer structure comprising an electroless plated copper layer formed on the base material layer, an electroplated copper layer formed on the electroless plated copper layer, an electroplated nickel layer formed on the electroplated copper layer, and an electroplated gold layer formed on the electroplated nickel layer.

Abstract translation: 一种用于在半导体元件和电路基板之间耦合的柔性布线基板。 柔性布线基板包括由绝缘和柔性材料制成的基材层和形成在基材层上的布线导体。 布线导体由至少一个化学镀层和至少一个形成在至少一个无电镀层上的电镀层形成。 布线导体与基材层的周边部分分开形成。 用于形成电镀层的用于电镀的电源线不会残留在基材层上。 布线导体具有例如包含在基材层上形成的无电镀铜层，形成在无电镀铜层上的电镀铜层，形成在电镀铜层上的电镀镍层的多层结构，以及 形成在电镀镍层上的电镀金层。

公开(公告)号：US20020157857A1

公开(公告)日：2002-10-31

申请号：US09575092

申请日：2000-05-19

Inventor： Noriaki Atou

IPC: H01B007/08

CPC classification number: H05K1/028 ,  H01L2224/50 ,  H05K3/28 ,  H05K2201/0394 ,  H05K2201/10681 ,  H01L2924/00012

Abstract: A tape carrier with high density wiring patterns and having high flexibility, a tape carrier package using such tape carrier, and a method of manufacturing them. The tape carrier comprises a base film made of an insulating material and having wiring patterns formed thereon. The tape carrier also has a bending area for bending the tape carrier therein. In the bending hole region, a plurality of round holes are formed regularly. Diameter of each of the holes is larger than a space between the wiring patterns in the bending area. Preferably, the centers of the holes are located at grid points of an assumed predetermined grid and at the intersections of diagonal lines connecting the grid points. Also, the center of each of the plurality of holes is located on the center line of a space between adjacent wiring patterns in the bending area.

Abstract translation: 具有高密度布线图案并且具有高柔性的带载体，使用这种带载体的带载体包装及其制造方法。 带载体包括由绝缘材料制成并具有形成在其上的布线图案的基膜。 带载体还具有用于在其中弯曲带载体的弯曲区域。 在弯曲孔区域中，规则地形成多个圆孔。 每个孔的直径大于弯曲区域中的布线图案之间的空间。 优选地，孔的中心位于假设的预定网格的网格点处，并且位于连接网格点的对角线的交点处。 此外，多个孔中的每一个的中心位于弯曲区域中的相邻布线图案之间的空间的中心线上。

公开(公告)号：US06424030B2

公开(公告)日：2002-07-23

申请号：US09863450

申请日：2001-05-24

Applicant: Watanabe Masayuki ,  Sugano Toshio ,  Tsukui Seiichiro ,  Ono Takashi ,  Wakashima Yoshiaki

Inventor： Watanabe Masayuki ,  Sugano Toshio ,  Tsukui Seiichiro ,  Ono Takashi ,  Wakashima Yoshiaki

IPC: H01L2302

CPC classification number: G11C5/02 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/49572 ,  H01L24/16 ,  H01L24/50 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05664 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/10515 ,  H05K2201/10681 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract translation: 在本发明中，存储芯片通过TAB（磁带自动键合）以堆叠的方式粘合在一起，并且由芯片和引线形成像SOP（小外线封装）的多存储器芯片和引线复合体，由此存储器 高封装密度的模块可以通过扁平封装技术实现。

公开(公告)号：US20020047978A1

公开(公告)日：2002-04-25

申请号：US09932026

申请日：2001-08-20

Inventor： Kazuhiko Fukuta ,  Tomohiko Iwane ,  Masahiko Monzen

IPC: G02F001/1333

CPC classification number: G02F1/13452 ,  G02B6/0073 ,  G02B6/0083 ,  G02F1/133615 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/361 ,  H05K2201/055 ,  H05K2201/10681 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor device of the present invention includes a film-like flexible substrate having formed thereon a wiring pattern, external connection terminals formed at both end portions of the flexible substrate; and a semiconductor element mounted on a surface side of the flexible substrate, wherein a folded part, which is folded down in U-shape to a back surface side of the flexible substrate, is formed in a fixed state at least at one end portion of the flexible substrate. With this structure, the semiconductor device is COF mounted, and, for example, in its application to a liquid crystal module wherein the semiconductor device is provided so as to face a liquid crystal panel, the external connection terminals of the flexible substrate can be connected to an inner surface of a module main body for a liquid crystal panel in a state the semiconductor element of the semiconductor device faces the inside of the module main body. As a result, since the semiconductor element can be mounted without being projected to the outside of the module main body, the liquid crystal module can be made thinner for the thickness of the semiconductor element.

Abstract translation: 本发明的半导体器件包括其上形成有布线图案的膜状柔性基板，形成在柔性基板的两端部的外部连接端子; 以及安装在柔性基板的表面侧的半导体元件，其中，以柔性基板的背面侧U形折叠的折叠部分至少在一个端部的 柔性基板。 利用这种结构，半导体器件被安装在COF上，并且例如在其应用于其中半导体器件被设置为面对液晶面板的液晶模块中，柔性基板的外部连接端子可以被连接 在半导体器件的半导体元件面向模块主体的内部的状态下，到达用于液晶面板的模块主体的内表面。 结果，由于半导体元件可以安装而不会突出到模块主体的外部，所以可以使半导体元件的厚度更薄化液晶模块。

公开(公告)号：US20020047133A1

公开(公告)日：2002-04-25

申请号：US09902154

申请日：2001-07-11

Applicant: ADVANCED DISPLAY INC.

Inventor： Kouki Nakahara ,  Hitoshi Morishita

IPC: H01L023/495 ,  H01L021/50 ,  H01L023/02

CPC classification number: H05K1/0281 ,  G02F1/13452 ,  H01L23/4985 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2924/01078 ,  H05K3/28 ,  H05K3/361 ,  H05K2201/0125 ,  H05K2201/09909 ,  H05K2201/10681 ,  H05K2201/2009

Abstract: A chip carrier film comprising a metal wiring formed on a surface of a base film, a first insulating film covering the metal wiring excluding a semiconductor chip connecting pad portion and a terminal connecting pad portion, a semiconductor chip connected to the semiconductor chip connecting pad portion of the metal wiring and mounted on the base film, and a second insulating film formed on a back face of the base film and having a different coefficient of curing shrinkage from that of the first insulating film. It is possible to obtain a chip carrier film capable of preventing the suspension of the base film from being generated by the self weight of the semiconductor chip when holding the base film by the delivery device and of carrying out mounting without a hindrance.

Abstract translation: 一种芯片载体膜，包括形成在基膜的表面上的金属布线，覆盖除了半导体芯片连接焊盘部分之外的金属布线的第一绝缘膜和端子连接焊盘部分，连接到半导体芯片连接焊盘部分的半导体芯片 的金属布线并安装在基膜上，第二绝缘膜形成在基膜的背面上，并且具有与第一绝缘膜的固化收缩率不同的固化收缩系数。 可以获得一种芯片载体膜，其能够防止当通过输送装置保持基膜时半导体芯片的自重产生基膜的悬浮，并且无障碍地进行安装。

公开(公告)号：US06357864B1

公开(公告)日：2002-03-19

申请号：US09464969

申请日：1999-12-16

Applicant: Carl Edmond Sullivan ,  Frank Edward Anderson ,  Paul Timothy Spivey ,  Kris Ann Reeves ,  Gary Raymond Williams ,  Jeanne Marie Saldanha Singh

Inventor： Carl Edmond Sullivan ,  Frank Edward Anderson ,  Paul Timothy Spivey ,  Kris Ann Reeves ,  Gary Raymond Williams ,  Jeanne Marie Saldanha Singh

IPC: B41J205

CPC classification number: B41J2/14072 ,  B41J2/14024 ,  H05K3/3494 ,  H05K3/363 ,  H05K3/4084 ,  H05K2201/0394 ,  H05K2201/10681 ,  H05K2201/10977 ,  H05K2203/0195 ,  H05K2203/1311

Abstract: The invention provides a printhead cartridge body contained within an inkjet printer which contains a tape automated bonding (TAB) circuit, having a unique architecture, electrically connected to a printhead heater chip and a printed circuit board (PCB). Moreover, the TAB circuit architecture is readily sealable by a variety of methods. The TAB circuit includes elongate apertures which have a length axis aligned perpendicular to electrical traces which run through the apertures. Each trace has a first end running through the apertures and being connected to a PCB by means of a hot bar soldering technique and the second end of the traces being connected to a printhead heater chip. An encapsulant layer substantially encloses the rectangular apertures and electrical connections preventing ink mist from contacting the connections. The TAB circuit design provides improvement in the manufacturing process and enables rework of connections without destroying the TAB circuit.

Abstract translation: 本发明提供了一种包含在喷墨打印机内的打印头墨盒体，其包含带状自动粘合（TAB）电路，其具有电连接到打印头加热器芯片和印刷电路板（PCB）的独特结构。 此外，TAB电路架构可以通过各种方法容易地密封。 TAB电路包括细长孔，其具有垂直于穿过孔的电迹线对准的长度轴。 每个迹线具有穿过孔的第一端，并且通过热棒焊接技术连接到PCB，并且迹线的第二端连接到打印头加热器芯片。 密封剂层基本上包围矩形孔和防止墨雾接触连接的电连接。 TAB电路设计提供了制造过程的改进，并能够重新连接连接而不破坏TAB电路。