公开(公告)号：US20140205864A1

公开(公告)日：2014-07-24

申请号：US14019486

申请日：2013-09-05

Applicant: SAMSUNG SDI CO., LTD.

Inventor： Sang-Il Yi ,  Moon-Gil Kang

IPC: H01M2/34

CPC classification number: H01M2/34 ,  H01M2/105 ,  H01M2/204 ,  H01M10/425 ,  H05K3/3426 ,  H05K3/4015 ,  H05K2201/0394 ,  H05K2201/10037 ,  H05K2201/1031 ,  H05K2201/10462 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10916 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613

Abstract: A rechargeable battery pack includes a plurality of battery cells, a connection tab electrically coupled to one or more terminals of the battery cells, a connection plate electrically coupled to the connection tab, and having an opening for accommodating a protruding portion of the connection tab, and a protective circuit module electrically coupled to the connection plate, and having a combination groove, wherein the connection plate is on a first surface of the protective circuit module to face the combination groove, and wherein the first surface of the protective circuit module faces the connection tab.

Abstract translation: 可再充电电池组包括多个电池单元，电连接到电池单元的一个或多个端子的连接凸片，电连接到连接凸片的连接板，并具有用于容纳连接凸片的突出部分的开口， 以及保护电路模块，电连接到所述连接板，并且具有组合凹槽，其中所述连接板位于所述保护电路模块的面对所述组合凹槽的第一表面上，并且其中所述保护电路模块的第一表面面向 连接标签。

公开(公告)号：US08547706B2

公开(公告)日：2013-10-01

申请号：US12873702

申请日：2010-09-01

Applicant: Hiroaki Tamura ,  Fumihiko Tokura ,  Michinao Nomura ,  Toshihiro Kusagaya ,  Kazuhiro Mizukami

Inventor： Hiroaki Tamura ,  Fumihiko Tokura ,  Michinao Nomura ,  Toshihiro Kusagaya ,  Kazuhiro Mizukami

IPC: H04L9/00

CPC classification number: H05K3/3426 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K2201/09136 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K2201/10787 ,  H05K2201/10909 ,  H05K2201/10946 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An electronic component includes: an electronic component body; and a lead secured to the electric component and including a projection portion defined by first and second inclined portions facing each other. The solder wettability of the first inclined portion is smaller than the solder wettability of the second inclined portion.

Abstract translation: 电子部件包括：电子部件主体; 以及固定到电气部件的引线，并且包括由彼此面对的第一和第二倾斜部分限定的突出部分。 第一倾斜部分的焊料润湿性小于第二倾斜部分的焊料润湿性。

公开(公告)号：US08378231B2

公开(公告)日：2013-02-19

申请号：US12510028

申请日：2009-07-27

Applicant: Kiyotaka Tsukada ,  Toshihiro Nomura ,  Daisuke Minoura

Inventor： Kiyotaka Tsukada ,  Toshihiro Nomura ,  Daisuke Minoura

IPC: H05K1/11

CPC classification number: H05K1/145 ,  H01L24/01 ,  H01L24/25 ,  H01L2224/2518 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/0204 ,  H05K3/284 ,  H05K3/306 ,  H05K2201/096 ,  H05K2201/10166 ,  H05K2201/10303 ,  H05K2201/10424 ,  H05K2201/10643 ,  H05K2201/10871 ,  H05K2201/10946 ,  Y10T29/4913 ,  Y10T29/49153 ,  H01L2924/00

Abstract: A semiconductor device includes wiring boards each having an insulating board, conductor circuits and through-holes, the insulating board having top and bottom surfaces, the conductor circuits formed on the top and bottom surfaces, the through holes penetrating the insulating board and electrically connecting the conductor circuits of the top and bottom surfaces; conductor posts each having flange, head and leg portions, the flange portion having first and second surfaces and having an external diameter larger than that of the through-hole, the head portion protruding from the first surface, the leg portion protruding from the second surface; and electronic components each having an electrode formed on one or more surfaces and connected to the leg portion. The head portion is inserted until the first surface of the flange portion comes into contact with the bottom surface of the wiring board and electrically connected at an inner wall of the through-hole.

Abstract translation: 半导体器件包括各自具有绝缘板，导体电路和通孔的布线板，所述绝缘板具有顶表面和底表面，所述导体电路形成在顶表面和底表面上，所述通孔穿过绝缘板并电连接 顶表面和底表面的导体电路; 导体柱各自具有凸缘，头部和腿部，凸缘部分具有第一和第二表面，并且具有比通孔大的外径，头部从第一表面突出，腿部从第二表面突出 ; 以及各自具有形成在一个或多个表面上并连接到所述腿部的电极的电子部件。 插入头部直到凸缘部分的第一表面与布线板的底表面接触并且在通孔的内壁处电连接。

公开(公告)号：US08233265B2

公开(公告)日：2012-07-31

申请号：US12617823

申请日：2009-11-13

Applicant: Hideki Otsuka ,  Kazuhiro Yoshida

Inventor： Hideki Otsuka ,  Kazuhiro Yoshida

IPC: H01G4/228 ,  H01G4/06

CPC classification number: H01G2/06 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30 ,  H05K3/3426 ,  H05K2201/10636 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613

Abstract: In a ceramic capacitor, first and second electrode terminals each include a bonded-to-substrate portion, a first bonded-to-electrode portion bonded to a first edge of one of first and second external electrodes, a second bonded-to-electrode portion bonded to a second edge of the one of first and second external electrodes and disposed at a distance from the first bonded-to-electrode portion in the first directions, and a connecting portion connecting the first and second bonded-to-electrode portions and the bonded-to-substrate portion. W1/W0 is about 0.3 or more, and h/L is about 0.1 or more.

Abstract translation: 在陶瓷电容器中，第一和第二电极端子各自包括接合到衬底部分，第一接合电极部分接合到第一和第二外部电极之一的第一边缘，第二接合电极部分 接合到第一外部电极和第二外部电极中的一个的第二边缘并且在第一方向上与第一接合电极部分设置一定距离，以及连接第一和第二接合电极部分和第二接合电极部分的连接部分， 键合到衬底部分。 W1 / W0为约0.3以上，h / L约为0.1以上。

公开(公告)号：US08039967B2

公开(公告)日：2011-10-18

申请号：US12686590

申请日：2010-01-13

Applicant: Yuichi Taguchi ,  Akinori Shiraishi ,  Mitsutoshi Higashi

Inventor： Yuichi Taguchi ,  Akinori Shiraishi ,  Mitsutoshi Higashi

IPC: H01L23/48 ,  H01L21/44 ,  H05K7/00

CPC classification number: B81B7/0074 ,  H01L24/16 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/78301 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19107 ,  H05K3/328 ,  H05K2201/10287 ,  H05K2201/10454 ,  H05K2201/10727 ,  H05K2201/10946 ,  H01L2924/00 ,  H01L2224/48

Abstract: A wiring substrate includes a silicon substrate, a through hole formed to penetrate the silicon substrate in a thickness direction, an insulating layer formed on both surfaces and side surfaces of the silicon substrate and an inner surface of the through hole, a penetration electrode formed in the through hole, a wiring layer formed on at least one surface of the silicon substrate and connected to the penetration electrode, and a metal wire terminal connected to the wiring layer and formed to extend from one surface of the silicon substrate to a side surface thereof. The metal wire terminal on the side surface of the electronic device is connected to the mounting substrate such that a substrate direction of the electronic device in which an electronic component is mounted on the wiring substrate intersects orthogonally with a substrate direction of the mounting substrate.

Abstract translation: 布线基板包括硅基板，形成为在厚度方向上穿透硅基板的通孔，形成在硅基板的两个表面和侧表面上的绝缘层和通孔的内表面，形成在 所述通孔，形成在所述硅衬底的至少一个表面上并连接到所述穿透电极的布线层和连接到所述布线层并形成为从所述硅衬底的一个表面延伸到其侧表面的金属线端子 。 电子装置的侧面上的金属线端子与安装基板连接，使得其中电子部件安装在布线基板上的电子装置的基板方向与安装基板的基板方向正交地交叉。

公开(公告)号：US08039944B2

公开(公告)日：2011-10-18

申请号：US12222255

申请日：2008-08-06

Applicant: Ted Ju

Inventor： Ted Ju

IPC: H01L23/48

CPC classification number: H05K7/1069 ,  H01R12/7076 ,  H05K3/301 ,  H05K3/325 ,  H05K2201/0311 ,  H05K2201/10598 ,  H05K2201/10719 ,  H05K2201/10946 ,  H05K2203/0271 ,  H05K2203/167

Abstract: An electrical connection device and assembly method thereof includes a substrate with a plurality of contacting portions arranged on a surface thereof; a chip module having a plurality of terminals inclining in one direction and compressed and contacted with the contacting portions correspondingly; at least one restricting structure which restricts the chip module to move a distance relative to the substrate depending on the compression deformation of the terminals when the terminals are contacted with the contacting portions; and at least one elastic element just producing deformation when the chip module moves the distance. When the terminals are compressed and contacted with the contacting portions, the restricting structure restricts the chip module to move the distance depending on the compression deformation of the terminals, so that the elastic element just produces deformation, which make the chip module only move in the direction opposite to the deformation direction of the terminals.

Abstract translation: 一种电连接装置及其组装方法，包括：具有布置在其表面上的多个接触部分的基板; 芯片模块，其具有多个端子，其一个方向倾斜并且相应地与所述接触部分压缩和接触; 至少一个限制结构，其限制当所述端子与所述接触部分接触时，所述芯片模块相对于所述基板相对于所述端子的压缩变形而相对于所述基板移动一定距离; 并且至少一个弹性元件刚好在芯片模块移动距离时产生变形。 当端子被压缩并与接触部分接触时，限制结构限制芯片模块根据端子的压缩变形移动距离，使得弹性元件刚刚产生变形，这使得芯片模块仅在 方向与端子的变形方向相反。

公开(公告)号：US07901995B2

公开(公告)日：2011-03-08

申请号：US11689558

申请日：2007-03-22

Applicant: Gabe Cherian

Inventor： Gabe Cherian

IPC: H01L21/60

CPC classification number: H05K3/3426 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49555 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L24/742 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1012 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45599 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73251 ,  H01L2224/73257 ,  H01L2224/81903 ,  H01L2224/85 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K3/308 ,  H05K2201/09418 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10825 ,  H05K2201/10871 ,  H05K2201/10946 ,  H05K2201/10977 ,  H05K2203/0769 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/72

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices.The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general.For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with.For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

Abstract translation: 本发明一般涉及电子设备之间的永久互连，例如集成电路封装，芯片，晶片和印刷电路板或基板或类似的电子设备。 更具体地说，涉及高密度电子设备。 本发明描述了可用于抵消热循环，冲击和振动以及恶劣环境条件的不良影响的手段和方法。 对于有铅器件，引线面向设备的热中心及其与之相互作用的系统。 对于无引线器件，安装元件被处理或准备好以控制沿着元件长度的焊料的迁移，以确保这些元件保持其期望的柔性。

公开(公告)号：US07806700B2

公开(公告)日：2010-10-05

申请号：US12344849

申请日：2008-12-29

Applicant: Charles V. DeSantis ,  David E. Burchell

Inventor： Charles V. DeSantis ,  David E. Burchell

IPC: H01R12/00

CPC classification number: H05K7/1053 ,  H01R12/57 ,  H01R12/7082 ,  H01R12/716 ,  H01R13/2435 ,  H01R13/2478 ,  H01R13/2485 ,  H01R13/41 ,  H05K3/3426 ,  H05K2201/10734 ,  H05K2201/10946 ,  Y02P70/613

Abstract: An adaptor for connecting ball grid array components to a circuit board with a leaded grid array joint, utilizing electric leads which can connect to a ball grid array on one end and a leaded grid array pad pattern on the opposite end.

Abstract translation: 一种用于将球栅阵列部件连接到具有引线格栅阵列接头的电路板的适配器，其利用可以连接到一端上的球栅阵列的电引线和相对端上的引线格栅阵列焊盘图案。

公开(公告)号：US20100136745A1

公开(公告)日：2010-06-03

申请号：US12698352

申请日：2010-02-02

Applicant: Sung-Wook Hwang

Inventor： Sung-Wook Hwang

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H05K1/181 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/3421 ,  H05K3/3447 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a package-on-package (POP) package is disclosed. The method includes preparing a first semiconductor package including a first substrate having external contact electrodes and a first semiconductor chip mounted on the first substrate, and preparing a second semiconductor package including a second substrate having external contact electrodes and a second semiconductor chip mounted on the second substrate. The method further includes forming lead lines in the second semiconductor package, the lead lines being electrically connected to the external contact electrodes of the second substrate, and stacking the second semiconductor package on the first semiconductor package and electrically connecting the external contact electrodes of the first substrate to the external contact electrodes of the second substrate using the lead lines.

Abstract translation: 公开了一种制造封装封装（POP）封装的方法。 该方法包括制备包括具有外部接触电极的第一基板和安装在第一基板上的第一半导体芯片的第一半导体封装，以及制备包括具有外部接触电极的第二基板和安装在第二基板上的第二半导体芯片的第二半导体封装 基质。 该方法还包括在第二半导体封装中形成引线，引线与第二衬底的外部接触电极电连接，并将第二半导体封装堆叠在第一半导体封装上，并电连接第一半导体封装的外部接触电极 使用引线将衬底施加到第二衬底的外部接触电极。

公开(公告)号：US07723834B2

公开(公告)日：2010-05-25

申请号：US11851284

申请日：2007-09-06

Applicant: Sung-Wook Hwang

Inventor： Sung-Wook Hwang

IPC: H01L23/495

CPC classification number: H05K1/181 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/3421 ,  H05K3/3447 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package-on-package (POP) package in which semiconductor packages are stacked using lead lines rather than conventional solder balls, and a fabricating method thereof are provided. According to the POP package and the fabricating method thereof of the present invention, the POP package is prevented from being short-circuited even when an underlying semiconductor package gets thicker and the POP package can sufficiently withstand deformation caused by post-fabrication warpage.

Abstract translation: 一种封装封装（POP）封装，其中使用引线而不是常规焊球堆叠半导体封装，并提供其制造方法。 根据本发明的POP封装及其制造方法，即使下面的半导体封装变厚并且POP封装能够充分地承受由后制造翘曲引起的变形，也可以防止POP封装短路。