公开(公告)号：US10013187B2

公开(公告)日：2018-07-03

申请号：US14829648

申请日：2015-08-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A mapping table accessing method for a rewritable non-volatile memory module is provided. The method includes: storing a mapping record corresponding to a first physical erasing unit into the first physical erasing unit, wherein the mapping record of the first physical erasing unit is a mapping relation of physical programming units in the first physical erasing unit. The method further includes: storing a mapping record corresponding to a second physical erasing unit into the second physical erasing unit, wherein the mapping record of the second physical erasing unit is a mapping relation of physical programming units in the second physical erasing unit. A size of the mapping record of the first physical erasing unit is different from a size of the mapping record of the second physical erasing unit.

公开(公告)号：US09965194B2

公开(公告)日：2018-05-08

申请号：US15333197

申请日：2016-10-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chin-Min Lin ,  Yueh-Hsuan Tsai ,  Tzu-Yin Lin

IPC: G11C16/34 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/349 ,  G11C16/3495

Abstract: A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and first data corresponding to the first write command, and writing the first data into a third physical erasing unit in first physical erasing units; and if a usage frequency of a fourth physical erasing unit in the first physical erasing units is less than a predetermined value, performing a data arrangement operation corresponding to the first write command to copy second data stored by the fourth physical to at least one of second physical erasing units.

公开(公告)号：US09947412B1

公开(公告)日：2018-04-17

申请号：US15603427

申请日：2017-05-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chun-Yang Hu

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C11/56

CPC classification number: G11C16/14 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C2211/5644

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes recording a plurality of characteristic parameters corresponding to a plurality of data to be programmed; arranging the data according to the characteristic parameters and identifying frequently-read data among the plurality of data according to the characteristic parameters, and programming the frequently-read data into a first physical programming unit of a rewritable non-volatile memory module, wherein a time for reading data from the first physical programming unit is less than a time for reading data from a second physical programming unit of the rewritable non-volatile memory module. Accordingly, the reading performance for the data can be effectively improved.

公开(公告)号：US20180101317A1

公开(公告)日：2018-04-12

申请号：US15361008

申请日：2016-11-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/04 ,  G06F3/0619 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  H03M13/2957

Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.

公开(公告)号：US09940189B2

公开(公告)日：2018-04-10

申请号：US14996214

申请日：2016-01-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Han Wang

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/0751 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A method and a system for data rebuilding and a memory control circuit unit thereof are provided. The method includes reading a plurality of physical-logical mapping information and a plurality of time information corresponding to the physical-logical mapping information stored in a rewritable non-volatile memory module. The method also includes sorting the plurality of physical-logical mapping information according to the plurality of time information corresponding to the physical-logical mapping information. The method further includes rebuilding a logical-physical mapping table according to the sorted plurality of physical-logical mapping information, and storing the rebuilt logical-physical mapping table into a buffer.

公开(公告)号：US09893912B1

公开(公告)日：2018-02-13

申请号：US15493139

申请日：2017-04-21

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Ting Wei ,  Wei-Yung Chen ,  Chao-Hsin Lin ,  Chih-Ming Chen

IPC: H04L25/03 ,  H04L27/26 ,  H04L27/01

CPC classification number: H04L27/2614 ,  H04L25/03019 ,  H04L27/01

Abstract: An exemplary embodiment provides an equalizer adjustment method. The method includes: performing a handshake operation to establish a connection with a host system by a memory storage device; in the handshake operation, receiving a first signal from the host system and performing a first modulation on the first signal by the adaptive equalizer; after the handshake operation is ended, receiving a second signal from the host system and performing a second modulation on the second signal according to a modulation result of the first modulation by the adaptive equalizer to compensate the second signal; and adjusting the adaptive equalizer according to a modulation result of the second modulation.

公开(公告)号：US09858366B2

公开(公告)日：2018-01-02

申请号：US13723114

申请日：2012-12-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Yi-Hong Huang ,  Huang-Heng Cheng

IPC: G06F17/50 ,  G06F13/16 ,  G06F13/10 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F9/455

CPC classification number: G06F17/5022 ,  G06F3/0679 ,  G06F9/455 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/105 ,  G06F13/1694 ,  G06F17/5027 ,  G06F2212/151 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: A simulating method for a flash memory and a simulator using the simulating method are provided. The simulator is configured to couple to a memory controller. The simulating method includes: setting a predetermined response condition; providing multiple command sets, wherein each of the command sets corresponds to a memory type; receiving a first command from the memory controller; identifying a second command in the command sets according to the first command; determining if the second command matches the predetermined response condition; obtaining a first signal corresponding to the second command according to the predetermined response condition; and, transmitting the first signal to the memory controller. Accordingly, the usage of the simulator is flexible.

公开(公告)号：US20170365328A1

公开(公告)日：2017-12-21

申请号：US15591114

申请日：2017-05-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G11C5/147 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/10

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

公开(公告)号：US09836121B2

公开(公告)日：2017-12-05

申请号：US14856563

申请日：2015-09-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Wei-Yung Chen ,  Yu-An Chen

IPC: G06F3/01 ,  A61B3/11

CPC classification number: G06F3/013 ,  A61B3/11

Abstract: An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.

公开(公告)号：US20170329381A1

公开(公告)日：2017-11-16

申请号：US15210905

申请日：2016-07-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Zeh-Yang Chew ,  Shou-Chih Lee ,  Po-Chun Hsieh ,  Yun-Chieh Chen ,  I-Chung Tsai

IPC: G06F1/30

CPC classification number: G06F1/30 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3275 ,  G11C5/14 ,  G11C29/021

Abstract: A memory storage device having a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a power management circuit and a memory control circuit unit is provided. When an external power supply device is electrically connected to the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device via the second connection interface unit, supplies an operation voltage to the rewritable non-volatile memory module and the memory control circuit unit and supplies the second power supply voltage to a host device. When the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit receives a first power supply voltage from the host device via the first connection interface unit and supplies the operation voltage to the memory control circuit unit and the rewritable non-volatile memory module.