公开(公告)号：US20190058006A1

公开(公告)日：2019-02-21

申请号：US16077603

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  James S. Clarke

IPC: H01L27/24 ,  H01L45/00

Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.

公开(公告)号：US20190043873A1

公开(公告)日：2019-02-07

申请号：US16122266

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Khaled Hasnat ,  Prashant Majhi ,  Deepak Thimmegowda

IPC: H01L27/11529 ,  H01L27/11573 ,  H01L29/786 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11531

Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20190041656A1

公开(公告)日：2019-02-07

申请号：US16022158

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Ali Khakifirooz ,  Prashant Majhi ,  Kunjal Parikh

IPC: G02B27/42 ,  H01L21/02 ,  H01L21/762 ,  G06T19/00 ,  H01L27/01 ,  G02B27/01

Abstract: Diffractive optical elements for wide field-of-view virtual reality devices and methods of manufacturing the same are disclosed. An example apparatus includes a substrate and a thin film stack including alternating layers of a first material and a second material. The thin film stack defines an annular protrusion. The annular protrusion has a stair-like profile. Top surfaces of separate ones of steps in the stair-like profile correspond to top surfaces of separate ones of the layers of the second material.

公开(公告)号：US10084058B2

公开(公告)日：2018-09-25

申请号：US15219193

申请日：2016-07-25

Applicant: INTEL CORPORATION

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/15 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/80 ,  H01L29/165 ,  H01L29/51 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

公开(公告)号：US20170250338A1

公开(公告)日：2017-08-31

申请号：US15595868

申请日：2017-05-15

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Niloy Mukherjee ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L45/00

CPC classification number: H01L45/122 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer. The present disclosure further provides a computing device. The computing device includes a motherboard, a processor mounted on the motherboard, and a communication chip fabricated on the same chip as the processor or mounted on the motherboard. The processor comprises a substrate, a first electrode, second electrode, and a RRAM layer which has a recess at the interface between the second electrode and RRAM oxide layer.

公开(公告)号：US12302643B2

公开(公告)日：2025-05-13

申请号：US17572437

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ilya Karpov ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma

IPC: H10D89/60 ,  H10D8/00

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises the first material, wherein the second structure is between the first and third structures.

公开(公告)号：US20250006695A1

公开(公告)日：2025-01-02

申请号：US18344260

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Adel A. Elsherbini ,  Brandon M. Rawlings ,  Kimin Jun ,  Omkar G. Karhade ,  Mohit Bhatia ,  Nitin A. Deshpande ,  Prashant Majhi ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer with a first die having a first contact; a second die having a second contact; and a pad layer, on the first and second dies, including a first pad and a second pad, where the first pad is coupled to and offset from the first contact in a first direction, and the second pad is coupled to and is offset from the second contact in a second direction different than the first direction; and a second layer including a third die having third and fourth contacts, where the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first pad, and the second contact is coupled to the fourth contact by the second pad.

公开(公告)号：US11764282B2

公开(公告)日：2023-09-19

申请号：US17465652

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Prashant Majhi ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/517 ,  H01L21/28176 ,  H01L29/401 ,  H01L29/4966 ,  H10B61/22 ,  H10B63/30

Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

公开(公告)号：US20230197614A1

公开(公告)日：2023-06-22

申请号：US17556422

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823475

Abstract: An integrated circuit structure includes a device layer including a plurality of transistors, a first interconnect feature vertically extending through the device layer, and an interconnect structure below the device layer. The interconnect structure below the device layer includes at least a second interconnect feature. In an example, the second interconnect feature is conjoined with the first interconnect feature. For example, the first and second interconnect features collectively form a continuous and monolithic body of conductive material.

公开(公告)号：US20230187507A1

公开(公告)日：2023-06-15

申请号：US17547980

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy ,  Aravind S. Killampalli

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit includes a body of semiconductor material. A source or drain region includes semiconductor material in contact with the body, where the semiconductor material of the source or drain region includes an outer region having a dopant concentration that is greater than a remaining region of the source or drain region, the outer region defining multiple contact surfaces of the source or drain region and extending into the source or drain region to a depth of at least 1 nm. A contact comprising a metal is on the multiple contact surfaces of the source or drain region. The dopant concentration of the outer region is continuous along the entire interface between the contact and the outer region, according to an example.