公开(公告)号：US07495928B2

公开(公告)日：2009-02-24

申请号：US11960161

申请日：2007-12-19

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H05K1/0243 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/023 ,  H05K1/112 ,  H05K3/242 ,  H05K2201/09227 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.

Abstract translation: 对于处理高速差分信号的诸如BGA或CSP的多端子半导体封装，将高速信号分配给插入器基板上的最内侧定位的电极焊盘，并且电极焊盘连接到 位于内插器基板上的最外侧的球垫。 通过这种布置，可以显着地减少电镀短截线的长度，并且可以最小化对信号波形的不利影响。 这种布置对于差分信号线特别有效。

公开(公告)号：US07375432B2

公开(公告)日：2008-05-20

申请号：US11382450

申请日：2006-05-09

Applicant: Erik W. Jensen

Inventor： Erik W. Jensen

IPC: H01L23/48 ,  H05K7/10 ,  H05K1/11

CPC classification number: H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09381 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: An interconnect includes a pad and at least two vias coupled to the pad. In one embodiment, the pad has five substantially straight edges, one via directly coupled to the pad by being formed substantially beneath the pad, and one via coupled to one of the five substantially straight edges by a tapered conductive segment. In another embodiment, the pad has three vias directly coupled to the pad and formed substantially beneath the pad. A method of forming an interconnect includes forming at least two vias in a substrate and coupling a pad to each of the at least two vias.

Abstract translation: 互连包括焊盘和耦合到焊盘的至少两个通孔。 在一个实施例中，焊盘具有五个基本上直的边缘，一个通孔通过基本上形成在焊盘下面而直接耦合到焊盘，并且一个通孔通过锥形导电段连接到五个基本上直的边缘中的一个。 在另一个实施例中，焊盘具有直接耦合到焊盘并且基本上形成在焊盘下面的三个通孔。 形成互连的方法包括在衬底中形成至少两个通孔并且将衬垫耦合到所述至少两个通孔中的每一个。

公开(公告)号：US07372149B2

公开(公告)日：2008-05-13

申请号：US11115213

申请日：2005-04-27

Applicant: Makoto Yamamoto ,  Eiji Suematsu

Inventor： Makoto Yamamoto ,  Eiji Suematsu

IPC: H01L23/34

CPC classification number: H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01Q21/065 ,  H01Q23/00 ,  H05K1/0206 ,  H05K1/0243 ,  H05K1/113 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/09072 ,  H05K2201/0979 ,  H05K2201/10727 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A high frequency semiconductor apparatus is provided which prevents characteristics of a high frequency semiconductor element from being deteriorated so that the high frequency semiconductor element can be made to operate stably. The high frequency semiconductor apparatus is so configured that heat generated by a high frequency semiconductor element is sequentially conducted through a grounding via hole to a first ground layer, a first via hole, a first ground sublayer, a bonding material layer, a second ground layer, a second via hole, and a third ground layer.

Abstract translation: 提供一种高频半导体装置，其防止高频半导体元件的特性劣化，使得可以使高频半导体元件稳定地工作。 高频半导体装置的结构是使高频半导体元件产生的热量依次通过接地通孔传导到第一接地层，第一通孔，第一接地子层，接合材料层，第二接地层 ，第二通孔和第三接地层。

公开(公告)号：US07367819B2

公开(公告)日：2008-05-06

申请号：US11548794

申请日：2006-10-12

Applicant: Yukinori Saka

Inventor： Yukinori Saka

IPC: H01R12/00

CPC classification number: H05K3/308 ,  H01R12/58 ,  H05K3/3447 ,  H05K2201/0979 ,  H05K2201/10856

Abstract: A terminal has a plurality of split solder portions inserted into through-holes in a printed circuit board. A first split solder portion has a cross-sectional shape such that four corners thereof contact an inner circumferential surface of the through hole for positioning, while a second split solder portion has a cross-sectional shape such that the portion is loosely inserted into the through hole without contacting an inner circumferential surface thereof. The plurality of split solder portions of the terminal are inserted into through holes having substantially equal diameters. The four corners of the first split solder portion contact the inner circumferential surface of the through hole for positioning and holding. The second split solder portion does not contact the inner circumferential surface of the through hole. The through holes are filled with solder to fix the split solder portions therein.

Abstract translation: 端子具有插入印刷电路板的通孔中的多个分割焊料部分。 第一分割焊料部分具有横截面形状，使得其四个角接触用于定位的通孔的内周表面，而第二分割焊接部分具有横截面形状，使得该部分松散地插入到通孔 孔，而不接触其内周面。 端子的多个分割焊接部分插入具有基本相同直径的通孔中。 第一分割焊料部分的四个角部与通孔的内周面接触以进行定位和保持。 第二分割焊接部不与通孔的内周面接触。 通孔填充有焊料以将分开的焊料部分固定在其中。

公开(公告)号：US07326860B2

公开(公告)日：2008-02-05

申请号：US11446669

申请日：2006-06-05

Applicant: Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

Inventor： Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/5384 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/0979 ,  H01L2924/00

Abstract: A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.

Abstract translation: 公开了具有接合面的多层基板。 衬底的一个实施例可以包括设置在接合表面上的旁路电容器连接焊盘。 旁路电容连接焊盘可能具有旁路电容器功率垫和旁路电容接地垫。 衬底还可以包括从旁路电容器功率焊盘路由到与接合表面间隔开的第一再分配层的多个电源通孔和从旁路电容器接地焊盘路由到第一再分配层的多个接地通孔。 衬底还可以包括根据功率和接地经由图案阵列从第一再分配层路由到第二再分布层的多个电源和接地通孔，其中多个接地通孔在第一再分配层处被点动到多个 电源通孔通过图案阵列形成电源和接地。

公开(公告)号：US20080003846A1

公开(公告)日：2008-01-03

申请号：US11715151

申请日：2007-03-06

Applicant: Shigenori Miyagawa

Inventor： Shigenori Miyagawa

IPC: H01R12/02

CPC classification number: H05K1/0271 ,  H05K1/0231 ,  H05K1/111 ,  H05K1/113 ,  H05K2201/09063 ,  H05K2201/0979 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

Abstract: According to one embodiment, a circuit board unit includes: a circuit board; and an electronic component that is surface-mounted on the circuit board. The electronic component includes a first electrode at one end and a second electrode at another end of the electronic component. The circuit board includes a plurality of penetrating holes penetrating through the circuit board at a position close to the first electrode and at a position close to the second electrode. The penetrating holes are arranged substantially symmetrically with respect to the electronic component.

Abstract translation: 根据一个实施例，电路板单元包括：电路板; 以及表面安装在电路板上的电子部件。 电子部件包括一端的第一电极和电子部件的另一端的第二电极。 电路板包括穿过电路板的多个穿透孔，靠近第一电极的位置和靠近第二电极的位置。 贯通孔相对于电子部件大致对称地配置。

公开(公告)号：US07183647B2

公开(公告)日：2007-02-27

申请号：US10709096

申请日：2004-04-13

Applicant: Kei Murayama ,  Masahiro Sunohara

Inventor： Kei Murayama ,  Masahiro Sunohara

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/81206 ,  H01L2224/81801 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/113 ,  H05K3/328 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10674 ,  H05K2203/0285 ,  H01L2924/00

Abstract: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

Abstract translation: 在本发明的布线基板中，电子部件的凸块通过超声波倒装芯片封装被接合到设置在绝缘膜上的布线图案的连接焊盘，通孔，通孔作为 在超声波倒装芯片封装被填充的支撑件支撑连接垫被布置在连接垫下面的绝缘膜中。

公开(公告)号：US20070034994A1

公开(公告)日：2007-02-15

申请号：US11475276

申请日：2006-06-27

Applicant: Yoon-hwa Choi

Inventor： Yoon-hwa Choi

IPC: H01L23/495

CPC classification number: H05K3/3442 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/0979 ,  H05K2201/10931 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a lead frame and a semiconductor package which allows reliable attachment of a small-sized semiconductor chip requiring a large number of leads to a board while providing high heat dissipation capability. The semiconductor package includes leads, each having a top plate extending inward from the outside edge of a frame and a plurality of pillar-shaped portions supporting the top plates, a semiconductor chip attached onto edge portions of the leads, wires connecting the leads with corresponding bonding pad on the semiconductor chip, and a molding material encapsulating the semiconductor chip and the wires and parts of the leads so as to the bottom surfaces of the leads are exposed. Further, some embodiments have a conductive pad exhibiting higher heat dissipation.

Abstract translation: 提供了一种引线框架和半导体封装件，其允许将需要大量引线的小尺寸半导体芯片可靠地附接到板，同时提供高散热能力。 半导体封装包括引线，每个引线具有从框架的外边缘向内延伸的顶板和支撑顶板的多个柱状部分，附接到引线的边缘部分的半导体芯片，将引线与相应的引线连接 接合焊盘，以及封装半导体芯片的模制材料以及引线的引线和引线的引线的底面露出。 此外，一些实施例具有呈现较高散热的导电垫。

公开(公告)号：US07176578B2

公开(公告)日：2007-02-13

申请号：US11258763

申请日：2005-10-26

Applicant: Hans Evald Goran Martin ,  Klas Anders Hjort ,  Mikael Peter Erik Lindberg

Inventor： Hans Evald Goran Martin ,  Klas Anders Hjort ,  Mikael Peter Erik Lindberg

IPC: H01L23/48

CPC classification number: H05K3/0041 ,  G01K2211/00 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/002 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2203/092 ,  H01L2924/00

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V 50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10–V60) are chosen having mutually different thermoelectric properties. A material surface-applied to the thin film substrate, coated on both sides (10a, 10b) of the thin film substrate (10), is distributed and/or adapted in order to allow the electrical interconnection of first vias, allocated the first material (M1), with second vias, allocated the second material (M2), and that a first via (V10) included in a series connection and a last via (V60) included in the series connection are serially co-ordinated in order to form an electric thermocouple (100) or other circuit arrangement.

Abstract translation: 本发明包括一种处理过的薄膜基片（10）及其方法，以便制造出一种柔性印刷电路卡，其具有多个微孔进入或通过薄膜基片并沿着相对表面电连接， 以形成电路。 第一个真正的纳米轨道填充有具有良好电性能的第一材料（M1），用于形成第一数量的这里计量的第一通孔（V 10，V 30，V 50）， 第二数量的真实纳米轨道填充有具有良好电性能的第二材料（M 2），用于形成第二数量的这里计数的第二通孔（V 20，V 40，V 60）。 选择所述第一和第二通孔（V 10 -V 60）的第一材料（M 1）和第二材料（M 2）具有相互不同的热电性质。 涂布在薄膜基板（10a，10b）的两侧（10a，10b）上的表面施加到薄膜基板上的材料被分布和/或适配，以便允许第一通孔的电互连， 具有第二通孔的第一材料（M 1）分配第二材料（M 2），并且串联连接中包括的第一通孔（V 10）和串联连接中包括的最后通孔（V 60）是串联的 为了形成电热电偶（100）或其他电路布置。

公开(公告)号：US07119285B2

公开(公告)日：2006-10-10

申请号：US10790310

申请日：2004-03-01

Applicant: Deok-heung Kim ,  Bong-hui Lee

Inventor： Deok-heung Kim ,  Bong-hui Lee

IPC: H05K1/00 ,  H05K1/03

CPC classification number: H05K1/028 ,  H05K3/28 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10666

Abstract: A flexible printed circuit board (FPCB) which prevents a short circuit due to a crack in a bending portion is provided. The FPCB includes an end portion, a bending portion extended from the end portion, and a circuit portion extended from the bending portion. The improved FPCB includes a base film which is flexible and comprises a first via-hole formed adjacent to the end portion and the bending portion and a second via-hole formed adjacent to the bending portion and the circuit portion, a first conductive layer formed on an outer surface of at least the end portion and the bending portion, a cover layer formed on the first conductive layer, a second conductive layer which is formed on an inner surface of the end portion and is electrically connected to the first conductive layer through the first via-hole, and a third conductive layer which is formed on an inner surface of the extension circuit portion and is electrically connected to the first conductive layer through the second via-hole.

Abstract translation: 提供一种柔性印刷电路板（FPCB），其防止由于弯曲部分的裂纹引起的短路。 FPCB包括端部，从端部延伸的弯曲部和从弯曲部延伸的电路部。 改进的FPCB包括柔性的基膜，包括邻近端部和弯曲部分形成的第一通孔和邻近弯曲部分和电路部分形成的第二通孔，形成在第一导电层上的第一导电层 至少所述端部和所述弯曲部的外表面，形成在所述第一导电层上的覆盖层，形成在所述端部的内表面上并通过所述第一导电层电连接到所述第一导电层的第二导电层 第一导电孔和第三导电层，其形成在延伸电路部分的内表面上，并通过第二通孔与第一导电层电连接。