公开(公告)号：US20120175160A1

公开(公告)日：2012-07-12

申请号：US13265323

申请日：2009-04-17

Applicant: Rachid M. Kadri ,  Stephen F. Contreras

Inventor： Rachid M. Kadri ,  Stephen F. Contreras

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/181 ,  G11C5/066 ,  H05K1/0237 ,  H05K1/114 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09227 ,  H05K2201/10189 ,  H05K2201/10545 ,  Y02P70/611 ,  Y10T29/49147

Abstract: A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

Abstract translation: 公开了一种方法和系统，以在大的存储器占用空间中减少迹线长度和电容。 当每个存储器通道使用更多的双列直插存储器模块（DIMM）连接器时，总线带宽可能会受到迹线长度和迹线电容的影响。 为了减少总体走线长度和跟踪电容，系统和方法使用棕榈树拓扑布局，即背对背DIMM放置，放置表面贴装技术（SMT）DIMM连接器（而不是通孔连接器 ）以印刷电路板（PCB）的每一面以镜面方式背对背。 与所有DIMM连接器放置在PCB一侧的常用传统拓扑布局相比，该系统和方法可以提高信号传播时间。

公开(公告)号：US08110929B2

公开(公告)日：2012-02-07

申请号：US12602462

申请日：2008-05-27

Applicant: Toshikazu Imaoka ,  Tetsuro Sawai ,  Kenichi Kobayashi ,  Atsushi Nakano

Inventor： Toshikazu Imaoka ,  Tetsuro Sawai ,  Kenichi Kobayashi ,  Atsushi Nakano

IPC: H01L23/48

CPC classification number: H05K1/141 ,  H01L24/73 ,  H01L25/0657 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/181 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/09136 ,  H05K2201/09418 ,  H05K2201/10545 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor module includes: a substrate having a wiring layer; a first rectangular-shaped semiconductor device mounted on one surface of the substrate; a second rectangular-shaped semiconductor device mounted on the other surface of the substrate. The first semiconductor device is arranged such that each side thereof is not parallel to that of the second semiconductor device, and that the first semiconductor device is superimposed on the second semiconductor device, when seen from the direction perpendicular to the surface of the substrate.

Abstract translation: 半导体模块包括：具有布线层的基板; 安装在所述基板的一个表面上的第一矩形半导体器件; 安装在所述基板的另一表面上的第二矩形半导体器件。 第一半导体器件布置成使得其每侧不与第二半导体器件的平行平行，并且当从垂直于衬底的表面的方向看时，第一半导体器件重叠在第二半导体器件上。

公开(公告)号：US20120008287A1

公开(公告)日：2012-01-12

申请号：US13064546

申请日：2011-03-30

Applicant: Young Jae Kim ,  Jae Woo Joung ,  Young Seuck Yoo

Inventor： Young Jae Kim ,  Jae Woo Joung ,  Young Seuck Yoo

IPC: H05K7/14 ,  H05K3/30 ,  H05K3/36 ,  H05K3/12

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H05K3/125 ,  H05K3/4664 ,  H05K2201/10545 ,  H05K2203/013 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: Disclosed are an electronic component module and a method of manufacturing the same. The electronic component module includes a first insulating layer having a first surface in which first circuit patterns are embedded, electronic components of different kinds, the electronic components being mounted on the first circuit patterns and having electrode parts placed in different locations, and a molding layer encompassing the electronic components. Accordingly, a thin-film type electronic component module having a thin insulating layer with a circuit pattern can be provided.

Abstract translation: 公开了电子部件模块及其制造方法。 电子部件模块包括第一绝缘层，其具有嵌入第一电路图形的第一表面，不同种类的电子部件，电子部件安装在第一电路图案上并且具有放置在不同位置的电极部分，以及模制层 包括电子元件。 因此，可以提供具有电路图案的薄绝缘层的薄膜型电子部件模块。

公开(公告)号：US08030752B2

公开(公告)日：2011-10-04

申请号：US12213796

申请日：2008-06-24

Applicant: Nobuyuki Ikeguchi ,  Keungjin Sohn ,  JoonSik Shin ,  Jung-Hwan Park

Inventor： Nobuyuki Ikeguchi ,  Keungjin Sohn ,  JoonSik Shin ,  Jung-Hwan Park

IPC: H01L23/04 ,  H01L23/12

CPC classification number: H05K1/144 ,  H01L23/13 ,  H01L23/145 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/0366 ,  H05K1/056 ,  H05K1/182 ,  H05K3/4608 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674

Abstract: A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.

Abstract translation: 制造半导体封装的方法可以包括：形成第一板; 在其中形成有至少一个空腔的第二板; 将第二板连接到第一板的两侧，使得第二板与第一板电连接; 以及通过将所述部件嵌入所述空腔中，通过倒装芯片方法将至少一个部件与所述第一板连接。 该方法可以防止对半导体芯片的损坏并降低制造成本，同时连接材料还可以减轻应力，防止板和半导体芯片中的开裂，同时​​防止诸如弯曲和翘曲的缺陷。 也可以避免温度变化引起的缺陷。 此外，不需要在半导体芯片与印刷电路板连接的部分中使用底部填充，这允许更容易的返工和降低成本。

公开(公告)号：US20110204992A1

公开(公告)日：2011-08-25

申请号：US12709038

申请日：2010-02-19

Applicant: John Robert MCINTYRE ,  Anthony Clement MANICONE

Inventor： John Robert MCINTYRE ,  Anthony Clement MANICONE

IPC: H01P5/18

CPC classification number: H01P5/18 ,  H04B1/52 ,  H05K1/0243 ,  H05K2201/1006 ,  H05K2201/10545

Abstract: An electronic device may include a printed circuit board (PCB) including a ground plane and having first and second opposing surfaces. The electronic device may also include a radio frequency (RF) directional coupler carried by the first surface of the PCB and including a housing and circuitry therein defining an input port, an output port, and first and second monitoring ports. A first monitoring circuit may be carried by the first surface of the PCB and connected to the first monitoring port. The electronic device may also include a via conductor connected to the second monitoring port and extending through the PCB to the second surface thereof. A second monitoring circuit may also be carried by the second surface of the PCB and connected to the via conductor.

Abstract translation: 电子设备可以包括包括接地平面并具有第一和第二相对表面的印刷电路板（PCB）。 电子设备还可以包括由PCB的第一表面承载的射频（RF）定向耦合器，并且包括限定输入端口，输出端口以及第一和第二监视端口的壳体和电路。 第一监视电路可以由PCB的第一表面承载并连接到第一监视端口。 电子设备还可以包括连接到第二监视端口并且穿过PCB延伸到其第二表面的通孔导体。 第二监视电路也可以由PCB的第二表面承载并连接到通孔导体。

公开(公告)号：US20110176346A1

公开(公告)日：2011-07-21

申请号：US13007086

申请日：2011-01-14

Applicant: Yukio KATAMURA

Inventor： Yukio KATAMURA

IPC: G11C5/02

CPC classification number: H01L25/0652 ,  H01L25/165 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/18161 ,  H01L2924/19106 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2203/1316 ,  H01L2224/05599

Abstract: According to one embodiment, semiconductor memory device including: a circuit substrate in which a circuit pattern is formed; a plurality of semiconductor memories mounted via a solder on both surfaces of the circuit substrate; a connector disposed at one end part of the circuit substrate for connection with a host device; and a resin mold part that seals the both surfaces of the circuit substrate. The resin mold part does not seal a region in which the connector is disposed and collectively seals regions in which the plurality of semiconductor memories are disposed.

Abstract translation: 根据一个实施例，半导体存储器件包括：形成电路图案的电路基板; 多个半导体存储器，其通过焊料安装在电路基板的两个表面上; 连接器，设置在电路基板的一个端部，用于与主机设备连接; 以及密封电路基板的两面的树脂模具部。 树脂模具部分不密封其中设置连接器的区域，并且集中地密封其中设置有多个半导体存储器的区域。

公开(公告)号：US07939909B2

公开(公告)日：2011-05-10

申请号：US11655915

申请日：2007-01-22

Applicant: Moon-chul Lee ,  In-sang Song ,  Young-tack Hong ,  Sung-hye Jeong ,  Jeong-yoo Hong ,  Byung-yoo Hong

Inventor： Moon-chul Lee ,  In-sang Song ,  Young-tack Hong ,  Sung-hye Jeong ,  Jeong-yoo Hong ,  Byung-yoo Hong

IPC: H01L29/00

CPC classification number: H01L27/016 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0744 ,  H01L28/10 ,  H01L28/40 ,  H01L2924/0002 ,  H03H7/00 ,  H03H7/0115 ,  H03H2001/0078 ,  H03H2001/0085 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/1006 ,  H05K2201/10545 ,  Y10S438/977 ,  H01L2924/00

Abstract: An LC device having a substrate, a support layer having upper and lower sides formed on the substrate, inductors formed on either the upper or lower side of the support layer, and capacitors formed in the opposite side of the support layer. The support layer may be formed of a low-k dielectric material, and a connection portion may be provided to connect the inductors and capacitors in the support layer. The inductors and capacitors are disposed in a stacked structure on the upper and lower sides of the low-k dielectric support layer on the substrate, so that space efficiency may be maximized on the substrate. The low-k dielectric support layer provides support between the inductors and capacitors so that substrate loss is minimized and a Q factor of the inductors is enhanced.

Abstract translation: 具有衬底的LC器件，在衬底上形成有上下侧的支撑层，形成在支撑层的上侧或下侧的电感器以及形成在支撑层的相对侧的电容器。 支撑层可以由低k介电材料形成，并且可以提供连接部分来连接支撑层中的电感器和电容器。 电感器和电容器以堆叠的结构设置在衬底上的低k电介质支撑层的上侧和下侧，使得在衬底上空间效率最大化。 低k电介质支撑层提供电感器和电容器之间的支撑，使得衬底损耗最小化并且电感器的Q因数增强。

公开(公告)号：US07929315B2

公开(公告)日：2011-04-19

申请号：US12694951

申请日：2010-01-27

Applicant: Seiji Hayashi ,  Hideho Inagawa

Inventor： Seiji Hayashi ,  Hideho Inagawa

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0231 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/0949 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract translation: 多层印刷电路板包括：第一表面层，包括半导体集成电路;第二表面层，包括旁路电容器，并且与第一表面层相对;主电源布线层;以及第一表面层， 和第二表面层。 在多层印刷电路板中，旁路电容器的一个端子连接到从主电源布线层到半导体集成电路的电源端子的布线路径的中点，并且从第一布线路径的阻抗 到旁路电容器的端子的主电源布线层高于从旁路电容器的端子到半导体集成电路的电源端子的第二布线路径的阻抗。

公开(公告)号：US07906840B2

公开(公告)日：2011-03-15

申请号：US12204677

申请日：2008-09-04

Applicant: Kanji Otsuka ,  Yutaka Akiyama

Inventor： Kanji Otsuka ,  Yutaka Akiyama

IPC: H01L23/02

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K2201/09672 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.

Abstract translation: 提供了一种半导体集成电路封装，印刷电路板，半导体装置和电源布线结构，即使在高频带宽下也能够实现稳定的电源和接地布线而不引起共振。 在封装的内部，电源布线和接地布线构成一对布线结构，其中电源布线和接地布线以预定的间隔并置，以便在它们之间建立电磁耦合。 多个对布线结构以这样的方式组合，即当在与布线延伸方向垂直的截面中观察时，该对布线组件呈现交错（方格）的结构。 优选地，像封装一样，硅芯片和印刷电路板中的每一个具有配置在内部的配线结构。

公开(公告)号：US20110058298A1

公开(公告)日：2011-03-10

申请号：US12555583

申请日：2009-09-08

Applicant: Joseph Kuczynski ,  Melissa K. Miller ,  Heidi Williams ,  Jing Zhang

Inventor： Joseph Kuczynski ,  Melissa K. Miller ,  Heidi Williams ,  Jing Zhang

IPC: H02H5/04

CPC classification number: H05K1/0201 ,  H05K1/0268 ,  H05K3/306 ,  H05K2201/044 ,  H05K2201/10053 ,  H05K2201/10151 ,  H05K2201/10189 ,  H05K2201/10545

Abstract: A method and apparatus directed to detecting and preventing excessive heating in power connectors is disclosed. In one embodiment, a system includes a power connector having an array of pins. A circuit board, such as a midplane of a blade server chassis, has an array of electrical vias passing through the circuit board that are arranged to receive the array of pins and at least one heat flux sensor positioned on one of the vias at the back of the midplane. The heat flux sensor is configured for generating an electrical signal in relation to an applied heat flux. A controller in communication with the heat flux sensor is configured for powering off the electrical power supply in response to the electrical signal reaching a setpoint corresponding to a selected heat flux threshold.

Abstract translation: 公开了一种用于检测和防止电力连接器中的过度加热的方法和装置。 在一个实施例中，系统包括具有引脚阵列的电源连接器。 电路板，例如刀片服务器机箱的中平面，具有通过电路板的电气通孔阵列，其布置成接收引脚阵列，并且至少一个热通量传感器位于后面的通孔中的一个上 的中平面。 热通量传感器被配置为相对于施加的热通量产生电信号。 与热通量传感器通信的控制器被配置为响应于电信号达到对应于所选择的热通量阈值的设定点来断电电源。