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    Process load lock apparatus, lift assemblies, electronic device processing systems, and methods of processing substrates in load lock locations
    81.
    发明授权
    Process load lock apparatus, lift assemblies, electronic device processing systems, and methods of processing substrates in load lock locations 有权
    过程负载锁定装置，电梯组件，电子设备处理系统以及在负载锁定位置处理衬底的方法

    公开(公告)号：US09355876B2

    公开(公告)日：2016-05-31

    申请号：US14203098

    申请日：2014-03-10

    Applicant: Applied Materials, Inc.

    Inventor： Paul B. Reuter ,  Ganesh Balasubramanian ,  JuanCarlos Rocha-Alvarez ,  Jeffrey B. Robinson ,  Dale Robert du Bois ,  Paul Connors

    IPC: B23Q3/16 ,  H01L21/67

    CPC classification number: H01L21/67178 ,  H01L21/67103 ,  H01L21/6719 ,  H01L21/67201 ,  H01L21/67313 ,  H01L21/67712 ,  Y10T29/49998

    Abstract: A process load lock apparatus is disclosed. The process load lock apparatus includes a load lock chamber adapted to couple between a mainframe section and a factory interface, the load lock chamber including an entry and an exit each having a slit valve, and a load lock process chamber located at a different level than the load lock chamber at the load lock location wherein the load lock process chamber is adapted to carry out a process on a substrate, such as oxide removal or other processes. Systems including the process load lock apparatus and methods of operating the process load lock apparatus are provided. A lift assembly including a containment ring is also disclosed, as are numerous other aspects.

    Abstract translation: 公开了一种加工装载锁定装置。 过程加载锁定装置包括适于联接在主机部分和工厂接口之间的装载锁定室，该装载锁定室包括一个入口和一个出口，每个入口和出口均具有狭缝阀，而负载锁定处理室位于与 在负载锁定位置处的负载锁定室，其中负载锁定处理室适于在衬底上执行诸如氧化物去除或其它过程的过程。 提供了包括过程加载锁定装置和操作加工装载锁定装置的方法的系统。 还公开了包括容纳环的电梯组件，以及许多其它方面。

    Profile shaping for control gate recesses
    82.
    发明授权
    Profile shaping for control gate recesses 有权

    公开(公告)号：US12211908B2

    公开(公告)日：2025-01-28

    申请号：US18460290

    申请日：2023-09-01

    Applicant: Applied Materials, Inc.

    Inventor： Akhil Singhal ,  Allison Yau ,  Sang-Jin Kim ,  Zeqiong Zhao ,  Zhijun Jiang ,  Deenesh Padhi ,  Ganesh Balasubramanian

    IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423

    Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.

    Chamber configurations and processes for particle control
    85.
    发明授权
    Chamber configurations and processes for particle control 有权

    公开(公告)号：US11670492B2

    公开(公告)日：2023-06-06

    申请号：US17071506

    申请日：2020-10-15

    Applicant: Applied Materials, Inc.

    Inventor： Fei Wu ,  Abdul Aziz Khaja ,  Sungwon Ha ,  Ganesh Balasubramanian ,  Vinay Prabhakar

    IPC: H01J37/32

    CPC classification number: H01J37/32871 ,  H01J37/32862 ,  H01J2237/335

    Abstract: Exemplary processing methods may include forming a plasma of a cleaning precursor in a remote region of a semiconductor processing chamber. The methods may include flowing plasma effluents of the cleaning precursor into a processing region of the semiconductor processing chamber. The methods may include contacting a substrate support with the plasma effluents for a first period of time. The methods may include lowering the substrate support from a first position to a second position while continuing to flow plasma effluents of the cleaning precursor. The methods may include cleaning the processing region of the semiconductor processing chamber for a second period of time.

    WAFER DE-CHUCKING DETECTION AND ARCING PREVENTION
    86.
    发明申请
    WAFER DE-CHUCKING DETECTION AND ARCING PREVENTION 有权

    公开(公告)号：US20220415695A1

    公开(公告)日：2022-12-29

    申请号：US17929144

    申请日：2022-09-01

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Ganesh Balasubramanian ,  Byung Chul Yoon ,  Hemant Mungekar

    IPC: H01L21/683 ,  H01L21/66 ,  H01L21/67 ,  H01J37/32

    Abstract: Methods and systems of detection of wafer de-chucking in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when de-chucking is detected. In one embodiment, a de-chucking detection method is based on measuring change in imaginary impedance of a plasma circuit, along with measuring one or both of reflected RF power and arc count. In another embodiment, a possibility of imminent de-chucking is detected even before complete de-chucking occurs by analyzing the signature change in imaginary impedance.

    Plasma density control on substrate edge
    87.
    发明授权
    Plasma density control on substrate edge 有权

    公开(公告)号：US11495440B2

    公开(公告)日：2022-11-08

    申请号：US16996004

    申请日：2020-08-18

    Applicant: Applied Materials, Inc.

    Inventor： Bhaskar Kumar ,  Prashanth Kothnur ,  Sidharth Bhatia ,  Anup Kumar Singh ,  Vivek Bharat Shah ,  Ganesh Balasubramanian ,  Changgong Wang

    IPC: H01J37/32

    Abstract: Embodiments of the present disclosure generally relate to apparatuses for reducing particle contamination on substrates in a plasma processing chamber. In one or more embodiments, an edge ring is provided and includes a top surface, a bottom surface opposite the top surface and extending radially outward, an outer vertical wall extending between and connected to the top surface and the bottom surface, an inner vertical wall opposite the outer vertical wall, an inner lip extending radially inward from the inner vertical wall, and an inner step disposed between and connected to the inner wall and the bottom surface. During processing, the edge ring shifts the high plasma density zone away from the edge area of the substrate to avoid depositing particles on the substrate when the plasma is de-energized.

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