公开(公告)号：US08043893B2

公开(公告)日：2011-10-25

申请号：US11855236

申请日：2007-09-14

Applicant: Bruce K. Furman ,  Jae-Woong Nah

Inventor： Bruce K. Furman ,  Jae-Woong Nah

IPC: H01L21/00 ,  H01L21/44 ,  H01L29/40

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/328 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0338 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.

Abstract translation: 一种用于形成电互连的电结构和方法。 该方法包括定位牺牲载体衬底，使得牺牲载体衬底内的非焊料金属芯结构的第一表面与第一导电焊盘接触。 第一表面被热压接合到第一导电焊盘。 从非焊接金属芯结构去除牺牲载体衬底。 在第二导电焊盘上形成焊料结构。 包括非焊料金属芯结构的第一衬底定位成使得非焊料金属芯结构的第二表面与焊料结构接触。 将焊料结构加热到足以使焊料结构熔化并在非焊接金属芯结构的第二表面和第二导电焊盘之间形成电和机械连接的温度。

公开(公告)号：US20110253422A1

公开(公告)日：2011-10-20

申请号：US13150691

申请日：2011-06-01

Applicant: Shigetsugu Muramatsu ,  Yasuhiko Kusama

Inventor： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC: H05K1/02

CPC classification number: H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

Abstract translation: 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。

公开(公告)号：US08033012B2

公开(公告)日：2011-10-11

申请号：US12165970

申请日：2008-07-01

Applicant: Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

Inventor： Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

IPC: H05K3/30

CPC classification number: H05K3/243 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2863 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/049 ,  H05K2203/0542 ,  H05K2203/0574 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49162 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49204

Abstract: A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads. In some embodiments, the test pads may be C4 test pads.

Abstract translation: 一种用于半导体测试探针卡的空间变压器及其制造方法。 该方法可以包括在具有限定第一间距间隔的多个第一接触测试焊盘的空间变压器基板上沉积第一金属层作为接地平面，在接地平面上沉积第一介电层，形成多个第二测试触点， 与所述第一间距间隔不同的第二间距间隔，以及在所述第一介电层上形成多个再分配引线，以将所述第一接触测试焊盘电耦合到所述第二接触测试焊盘。 在一些实施例中，再分配引线可以直接构建在空间变换器基板上。 该方法可以在一个实施例中用于重新制造现有空间变压器以产生具有小于原始测试焊盘的间距间距的细间距测试焊盘。 在一些实施例中，测试焊盘可以是C4测试焊盘。

公开(公告)号：US20110239458A1

公开(公告)日：2011-10-06

申请号：US13159773

申请日：2011-06-14

Applicant: Bruce K. Furman ,  Jae-Woong Nah

Inventor： Bruce K. Furman ,  Jae-Woong Nah

IPC: H05K3/10

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/328 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0338 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.

Abstract translation: 一种用于形成电互连的电结构和方法。 该方法包括定位牺牲载体衬底，使得牺牲载体衬底内的非焊料金属芯结构的第一表面与第一导电焊盘接触。 第一表面被热压接合到第一导电焊盘。 从非焊接金属芯结构去除牺牲载体衬底。 在第二导电焊盘上形成焊料结构。 包括非焊料金属芯结构的第一衬底定位成使得非焊料金属芯结构的第二表面与焊料结构接触。 将焊料结构加热到足以使焊料结构熔化并在非焊接金属芯结构的第二表面和第二导电焊盘之间形成电和机械连接的温度。

公开(公告)号：US20110212631A1

公开(公告)日：2011-09-01

申请号：US13034066

申请日：2011-02-24

Applicant: Mituru IIDA

Inventor： Mituru IIDA

IPC: H01R12/79

CPC classification number: H01R12/62 ,  H01R12/52 ,  H01R12/55 ,  H05K1/141 ,  H05K3/3442 ,  H05K3/365 ,  H05K2201/0367 ,  H05K2201/0397 ,  H05K2201/09063 ,  H05K2201/091 ,  H05K2201/09181 ,  H05K2201/1059 ,  H05K2201/2009

Abstract: A female circuit board for use with a male circuit board has electrically conductive projections. The female circuit board includes a flexible insulating film. The flexible insulating film includes insertion portions into which the conductive projections of the male circuit board are allowed to be inserted. Each of the insertion portions includes a plurality of slits communicating with each other at the center of each of the insertion portions. The flexible insulating film further includes electrically conduction portions for making contact with the conductive projections to come into conduction with the male circuit board. The conduction portions are disposed around the insertion portions on the surface of the female circuit board facing the male circuit board when the female circuit board is in contact with the male circuit board. The conduction portions conform in shape to the insertion portions.

Abstract translation: 与阳电路板一起使用的母电路板具有导电突起。 阴电路板包括柔性绝缘膜。 柔性绝缘膜包括允许插入阳电路板的导电突起的插入部分。 每个插入部分包括在每个插入部分的中心处彼此连通的多个狭缝。 柔性绝缘膜还包括用于与导电突起接触以与阳电路板导通的导电部分。 当阴电路板与阳电路板接触时，导电部分设置在阴电路板的面对阳电路板的表面上的插入部分周围。 导电部分的形状与插入部分一致。

公开(公告)号：US08003893B2

公开(公告)日：2011-08-23

申请号：US12145802

申请日：2008-06-25

Applicant: Hisao Miura ,  Shinji Murata

Inventor： Hisao Miura ,  Shinji Murata

IPC: H05K1/03

CPC classification number: H05K3/4007 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09781 ,  H05K2201/2009

Abstract: A multilayer ceramic circuit board includes ceramic wiring layers which are stacked together, one or two or more lifting layers which have a planar shape and which are disposed as an inner layer inside the stacked ceramic wiring layers or as a lower layer lower than a bottom ceramic wiring layer, and a protruding portion formed on a surface of a top ceramic wiring layer due to the disposition of the one or two or more lifting layers. The protruding portion smoothly protrudes and has a large area and high flatness. The multilayer ceramic circuit board is formed by disposing lifting layers as an inner layer of a plurality green sheets or as a lower layer lower than a bottom green sheet, and firing under pressure the resulting laminate in a state constrained by an elastic constraining sheet and a rigid constraining sheet.

Abstract translation: 多层陶瓷电路板包括堆叠在一起的陶瓷布线层，一个或两个以上的提升层，其具有平面形状，并且作为内层设置在堆叠的陶瓷布线层内部或作为比底部陶瓷 布线层和由于一个或两个或更多个提升层的布置而形成在顶部陶瓷布线层的表面上的突出部分。 突出部分平滑地突出并且具有大的面积和高的平坦度。 多层陶瓷电路板通过将提升层设置为多个生片的内层或低于底部生片的下层而形成，并且在受到弹性约束片约束的状态下在压力下烧结所得到的层压体， 刚性约束片。

公开(公告)号：US07981728B2

公开(公告)日：2011-07-19

申请号：US12382293

申请日：2009-03-12

Applicant: Soon-Jin Cho

Inventor： Soon-Jin Cho

IPC: H01L21/00

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H05K1/0206 ,  H05K3/06 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/1536 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: A coreless substrate having a plurality of function pads, etched from a metal sheet and having a protruded shape; an insulating layer, the insulating layer being formed on one side of the function pads, a circuit corresponding to a pattern being formed on the insulating layer, a via hole being formed on the insulating layer to electrically connect the function pads and the circuit; and a solder resist, being formed on the insulating layer to protect the surface of the insulating layer. The coreless substrate has a signal delivery characteristic that is improved by eliminating the inner via hole.

Abstract translation: 一种无芯基板，具有从金属板蚀刻并具有突出形状的多个功能垫; 绝缘层，所述绝缘层形成在所述功能焊盘的一侧上，对应于在所述绝缘层上形成的图案的电路，形成在所述绝缘层上以电连接所述功能焊盘和所述电路的通孔; 和阻焊层，形成在绝缘层上以保护绝缘层的表面。 无芯基板具有通过消除内通孔而改善的信号传递特性。

公开(公告)号：US07971973B2

公开(公告)日：2011-07-05

申请号：US11520582

申请日：2006-09-14

Applicant: Yasuhiko Maeda

Inventor： Yasuhiko Maeda

IPC: B41J2/05

CPC classification number: H05K3/361 ,  B41J2/14233 ,  B41J2002/14258 ,  B41J2002/14491 ,  H05K3/321 ,  H05K3/4611 ,  H05K2201/0367 ,  H05K2201/09472

Abstract: The electrical connection structure includes: a first substrate which has a first electrode part; a second substrate which has a second electrode part opposing the first electrode part, and a wiring pattern connected to the second electrode part; an insulating cavity substrate which is disposed between the first substrate and the second substrate and has a through hole in a position corresponding to the first electrode part, the through hole being deeper that a sum of a height of the first electrode part and a height of the second electrode part and having an opening surface area not smaller that an area of the first electrode part; and conductive material which is filled in the through hole.

Abstract translation: 电连接结构包括：具有第一电极部分的第一基板; 具有与所述第一电极部相对的第二电极部的第二基板和与所述第二电极部连接的布线图案。 绝缘腔基板，设置在所述第一基板和所述第二基板之间，并且在与所述第一电极部对应的位置具有通孔，所述通孔比所述第一电极部的高度和所述第一电极部的高度 所述第二电极部分具有不小于所述第一电极部分的面积的开口表面积; 以及填充在通孔中的导电材料。

公开(公告)号：US07971352B2

公开(公告)日：2011-07-05

申请号：US12213465

申请日：2008-06-19

Applicant: Shuhichi Okabe ,  Jin-Yong An ,  Seok-Kyu Lee ,  Soon-Oh Jung ,  Jong-Kuk Hong ,  Hae-Nam Seo

Inventor： Shuhichi Okabe ,  Jin-Yong An ,  Seok-Kyu Lee ,  Soon-Oh Jung ,  Jong-Kuk Hong ,  Hae-Nam Seo

IPC: H01R9/00 ,  H05K3/00

CPC classification number: H05K3/4682 ,  H05K3/108 ,  H05K3/205 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2203/0376 ,  H05K2203/043 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149

Abstract: A method of manufacturing a printed circuit board having solder balls. The method may include: stacking a second carrier, in which at least one hole is formed, over one side of a first carrier; forming at least one solder bump by filling the hole with a conductive material; forming a circuit pattern layer, which is electrically connected with the solder bump, on the second carrier; and exposing the solder bump by removing the first carrier and the second carrier. Using this method, uniform hemispherical solder balls with fine pitch can be formed as a part of the manufacturing process, without having to attach the solder balls separately. Carriers may be used to serve as supports during the manufacturing process, whereby deformations can be prevented in the board.

Abstract translation: 一种制造具有焊球的印刷电路板的方法。 该方法可以包括：在第一载体的一侧堆叠形成有至少一个孔的第二载体; 通过用导电材料填充孔而形成至少一个焊料凸块; 在所述第二载体上形成与所述焊料凸块电连接的电路图案层; 以及通过去除所述第一载体和所述第二载体来暴露所述焊料凸块。 使用这种方法，可以形成具有细间距的均匀的半球形焊球作为制造过程的一部分，而不必分别附接焊球。 可以在制造过程中使用载体作为支撑体，从而可以防止板的变形。

公开(公告)号：US07964971B2

公开(公告)日：2011-06-21

申请号：US12346566

申请日：2008-12-30

Applicant: Warren M. Farnworth

Inventor： Warren M. Farnworth

IPC: H01L29/40

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/243 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/0367 ,  H05K2201/0373 ,  H01L2224/13099 ,  H01L2224/05099

Abstract: A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they are all joined. The flexibility of the interconnect may be varied by controlling the column dimensions, height, aspect ratio, number of columns, column material and by applying a supporting layer of dielectric material to a controlled depth about the base of the columns. A large number of interconnects may be formed on a wafer, partial wafer, single die, interposer, circuit board, or other substrate.

Abstract translation: 用于微电子衬底的柔性柱互连件包括从接合焊盘或其它导电端子以基本上相互平行布置的方式延伸的多个导电柱，在接合焊盘和接触焊盘的形式的公共盖之间提供冗余的电流路径， 他们都加入了。 互连的灵活性可以通过控制柱尺寸，高度，纵横比，列数，柱材料以及通过将介电材料的支撑层施加到围绕柱的底部的受控深度来改变。 可以在晶片，部分晶片，单芯片，插入器，电路板或其它基板上形成大量互连。