公开(公告)号：US20080251279A1

公开(公告)日：2008-10-16

申请号：US11946360

申请日：2007-11-28

Applicant: Shigetsugu Muramatsu ,  Yasuhiko Kusama

Inventor： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC: H05K3/00 ,  H05K1/00

CPC classification number: H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

Abstract translation: 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。

公开(公告)号：US07394341B2

公开(公告)日：2008-07-01

申请号：US11017884

申请日：2004-12-22

Applicant: Koji Shimoyama ,  Nobuya Matsutani ,  Yuji Mido ,  Michio Ohba ,  Akihiko Ibata

Inventor： Koji Shimoyama ,  Nobuya Matsutani ,  Yuji Mido ,  Michio Ohba ,  Akihiko Ibata

IPC: H01F5/00

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/107 ,  H05K3/244 ,  H05K3/4614 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2201/09036

Abstract: A coil electric conductor has an insulating substrate, a first conductive layer, and a second conductive layer. The first conductive layer is formed at a depression provided on a face of the insulating substrate. The second conductive layer is formed on the first conductive layer with the first conductive layer interposed between the second conductive layer and the insulating substrate. This construction realizes a coil electric conductor having a highly precisely uniformized cross-sectional shape.

Abstract translation: 线圈电导体具有绝缘基板，第一导电层和第二导电层。 第一导电层形成在设置在绝缘基板的表面上的凹陷处。 第二导电层形成在第一导电层上，第一导电层置于第二导电层和绝缘基板之间。 这种结构实现了具有高精度均匀横截面形状的线圈导电体。

公开(公告)号：US07383630B2

公开(公告)日：2008-06-10

申请号：US11166058

申请日：2005-06-24

Applicant: Yu-Nung Shen

Inventor： Yu-Nung Shen

IPC: H01K3/10 ,  H05K3/02

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/0002 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/246 ,  H05K3/28 ,  H05K3/388 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09881 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for making a circuit plate includes: forming first holes in an insulating layer; forming a conductive layer on the insulating layer such that a portion of the conductive layer fills the first holes; grinding the conductive layer such that the portion of the conductive layer remains in the first holes to form a pattern of conductive traces; forming a dielectric protective layer that covers the insulating layer and the conductive traces; forming a pattern of second holes in the protective layer such that a portion of each of the conductive traces is accessible through a respective one of the second holes; and forming conductive bumps that are respectively connected to the conductive traces.

Abstract translation: 制造电路板的方法包括：在绝缘层中形成第一孔; 在所述绝缘层上形成导电层，使得所述导电层的一部分填充所述第一孔; 研磨导电层，使得导电层的部分保留在第一孔中以形成导电迹线图案; 形成覆盖绝缘层和导电迹线的介电保护层; 在保护层中形成第二孔的图案，使得每个导电迹线的一部分可通过相应的一个第二孔接近; 以及形成分别连接到导电迹线的导电凸块。

公开(公告)号：US20080029894A1

公开(公告)日：2008-02-07

申请号：US11808028

申请日：2007-06-06

Applicant: Hsien-Shou Wang

Inventor： Hsien-Shou Wang

IPC: H01L23/532 ,  H01L21/44

CPC classification number: H05K3/4007 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/007 ,  H05K3/107 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/1572 ,  H01L2924/00

Abstract: The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer comprises a first surface and a second surface, plural vias are formed in the first surface, the circuit layer is formed on the first surface and in the vias to electrically connect to another circuit layer disposed under the dielectric layer; a metal layer embedded in the exposed second surface of the circuit build-up structure without protruding the exposed second surface and connected to the circuit layer; and two solder masks disposed on the exposed first surface and the exposed second surface of the circuit build-up structure, wherein the solder masks have plural openings to separately expose part of the circuit layer and the metal layer functioning as conductive pads.

Abstract translation: 本发明提供了一种倒装芯片封装基板和一种用于制造倒装芯片封装基板的方法，该封装基板包括至少包括介电层和至少电路层的电路组合结构，其中每个电介质层包括第一 表面和第二表面，在第一表面中形成多个通孔，电路层形成在第一表面和通孔中，以电连接到设置在电介质层下方的另一个电路层; 嵌入在电路堆积结构的暴露的第二表面中的金属层，而不突出暴露的第二表面并连接到电路层; 以及设置在暴露的第一表面和电路堆积结构的暴露的第二表面上的两个焊接掩模，其中焊料掩模具有多个开口以分别暴露电路层的一部分和用作导电焊盘的金属层。

公开(公告)号：US20070221942A1

公开(公告)日：2007-09-27

申请号：US11723235

申请日：2007-03-19

Applicant: Gi Ho Jeong ,  Si Young Yang ,  Jae Wook Kwon ,  Jeong Hoon Park ,  Hyun Ju Yi ,  Choon Keun Lee

Inventor： Gi Ho Jeong ,  Si Young Yang ,  Jae Wook Kwon ,  Jeong Hoon Park ,  Hyun Ju Yi ,  Choon Keun Lee

IPC: H01L33/00 ,  H01L29/22

CPC classification number: H01L33/62 ,  H01L2224/48091 ,  H01L2924/01019 ,  H05K1/056 ,  H05K3/045 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/10106 ,  H05K2203/0108 ,  H05K2203/025 ,  Y10T29/49158 ,  Y10T29/49172 ,  H01L2924/00014

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 μm or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract translation: 本文公开了一种没有印刷电路板（PCB）的发光二极管（LED）背光单元。 LED背光单元包括底盘，绝缘树脂层和一个或多个光源模块。 绝缘树脂层形成在底座上。 电路图案形成在绝缘树脂层上。 光源模块安装在绝缘树脂层上并电连接到电路图案。 绝缘树脂层的厚度为200μm以下，通过在底盘上层叠固体膜绝缘树脂或者通过使用旋转涂布或刮刀涂布的成型方法将液体绝缘树脂施加到底架而形成。 此外，通过用金属材料填充绝缘树脂层的雕刻电路图案来形成电路图案。

公开(公告)号：US20070194456A1

公开(公告)日：2007-08-23

申请号：US11360200

申请日：2006-02-23

Applicant: Charles Cohn

Inventor： Charles Cohn

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/4985 ,  H01L2224/16225 ,  H05K1/0204 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/064 ,  H05K3/202 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0376 ,  Y02P70/611

Abstract: A circuit substrate for attachment to an integrated circuit chip comprises an electrical trace, a mounting pad and a dielectric layer. The mounting pad has a first surface, one or more sidewalls and a second surface. The first surface is attached to the electrical trace. The dielectric layer substantially covers the one or more sidewalls of the mounting pad and has an uppermost surface that is substantially coplanar with the second surface of the mounting pad.

Abstract translation: 用于附接到集成电路芯片的电路基板包括电迹线，安装焊盘和介电层。 安装垫具有第一表面，一个或多个侧壁和第二表面。 第一个表面附着在电气痕迹上。 电介质层基本上覆盖安装焊盘的一个或多个侧壁，并且具有与安装焊盘的第二表面基本共面的最上表面。

公开(公告)号：US20070171621A1

公开(公告)日：2007-07-26

申请号：US11626379

申请日：2007-01-24

Applicant: Tsung-Yuan Chen

Inventor： Tsung-Yuan Chen

IPC: H05K7/00 ,  H05K3/10

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/0361 ,  H05K2203/0723 ,  Y10T29/49155 ,  Y10T156/1028

Abstract: A process for fabricating a circuit board with an embedded passive component is provided. First, an electrode-patterned layer having electrodes is formed on a surface of a conductive layer. Then, a passive component material is filled in the intervals between the electrodes. Then, the conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. Next, the conductive layer is patterned to form a circuit layer.

Abstract translation: 提供了一种用于制造具有嵌入式无源元件的电路板的工艺。 首先，在导电层的表面上形成具有电极的电极图案层。 然后，在电极之间的间隔中填充无源元件材料。 然后，将导电层和电极图案层层压到电介质层，其中电极图案层被嵌入在电介质层中。 接下来，对导电层进行图案化以形成电路层。

公开(公告)号：US07232608B2

公开(公告)日：2007-06-19

申请号：US11122138

申请日：2005-05-04

Applicant: Masahito Fujihara ,  Masahiro Kouno ,  Kazuya Edamura

Inventor： Masahito Fujihara ,  Masahiro Kouno ,  Kazuya Edamura

IPC: B32B9/00

CPC classification number: H05K3/1283 ,  B82Y30/00 ,  H05K3/102 ,  H05K3/107 ,  H05K3/1208 ,  H05K2201/0116 ,  H05K2201/0376 ,  H05K2203/0557 ,  H05K2203/082 ,  Y10T428/25 ,  Y10T428/30

Abstract: The present invention provides a conductive material having superior bending property and superior bending resistant property and a method for manufacturing the same. This object is achieved by a conductive material comprising a substrate and a conductive portion formed within the substrate, wherein a change ratio in the electric resistance values before and after a bending resistant property test, in which the conductive portion is bent by 180 degrees and a load of 1 kg/cm2 is imposed on the bent portion for one hour, is set within a range of ±10%.

Abstract translation: 本发明提供具有优异的弯曲性和优异的抗弯曲性的导电材料及其制造方法。 该目的通过包括基板和形成在基板内的导电部分的导电材料来实现，其中导电部分弯曲180度的抗弯曲性试验之前和之后的电阻值的变化率和 在弯曲部分施加1kg / cm 2的负荷1小时，设定在±10％的范围内。

公开(公告)号：US20060057341A1

公开(公告)日：2006-03-16

申请号：US11229394

申请日：2005-09-15

Applicant: Kenichi Kawabata ,  Hisayuki Abe ,  Masashi Katsumata

Inventor： Kenichi Kawabata ,  Hisayuki Abe ,  Masashi Katsumata

IPC: B32B3/00 ,  C25D5/02

CPC classification number: H05K1/0265 ,  C25D5/022 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/064 ,  H05K3/107 ,  H05K3/108 ,  H05K3/20 ,  H05K3/243 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2203/0384 ,  H05K2203/0542 ,  H05K2203/1476 ,  Y10T428/24917

Abstract: A multilayer substrate according to the present invention includes a plurality of laminated insulating layers and conductive patterns formed between the respective insulating layers. The conductive patterns include a first conductive pattern having a predetermined thickness and a second conductive pattern thicker than the first conductive pattern. The first and second conductive patterns are located in the same layer. The first conductive pattern is formed by pattern-etching a conductive layer having a uniform thickness by the subtractive method. The second conductive pattern is formed by forming a pattern-forming groove and then filling the inside of the pattern-forming groove with a conductive material simultaneously with forming a via hole. The first conductive pattern is suitable for an LC pattern for a high-frequency circuit requiring small variations in the width and the thickness of the pattern as well as accuracy in the thickness relative to an insulating pattern, and for a normal conductive pattern requiring impedance matching. The second conductive pattern is suitable for an L pattern for a choke coil.

Abstract translation: 根据本发明的多层基板包括多个层叠绝缘层和形成在各绝缘层之间的导电图案。 导电图案包括具有预定厚度的第一导电图案和比第一导电图案更厚的第二导电图案。 第一和第二导电图案位于同一层中。 通过减法法对具有均匀厚度的导电层进行图案蚀刻来形成第一导电图案。 第二导电图案通过形成图案形成槽，然后在形成通孔的同时用导电材料填充图案形成槽的内部而形成。 第一导电图案适用于要求图案的宽度和厚度的小变化以及相对于绝缘图案的厚度精度的高频电路的LC图案，以及需要阻抗匹配的正常导电图案 。 第二导电图案适用于扼流线圈的L图案。

公开(公告)号：US20060014403A1

公开(公告)日：2006-01-19

申请号：US11175448

申请日：2005-07-07

Applicant: Daisuke Sakurai ,  Kazuhiro Nishikawa ,  Norihito Tsukahara

Inventor： Daisuke Sakurai ,  Kazuhiro Nishikawa ,  Norihito Tsukahara

IPC: H01R12/00

CPC classification number: H05K3/361 ,  H01R12/52 ,  H01R43/0207 ,  H05K3/107 ,  H05K2201/0129 ,  H05K2201/0376 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/065

Abstract: First circuit board 10 including first resin base material 12 which is softened by heating and has a fusing property, and a plurality of first conductor patterns 14 formed on a surface of first resin base material 12, and second circuit board 20 on which a plurality of second conductor patterns 24 are formed with the same pitch as that of first conductor patterns 14 are provided. In the configuration, first conductor patterns 14 and second conductor patterns 24 are brought into mechanical contact with each other to provide electrical conduction; first resin base material 12 covers first conductor patterns 14 and second conductor patterns 24 and is bonded to second resin base material 22 of second circuit board 20, thereby connecting first circuit board 10 and second circuit board 20 to each other.

Abstract translation: 第一电路板10包括通过加热软化并具有熔融特性的第一树脂基材12和形成在第一树脂基材12的表面上的多个第一导体图案14和第二电路板20， 形成与第一导体图案14相同的间距的第二导体图案24。 在该结构中，第一导体图案14和第二导体图案24彼此机械接触以提供导电; 第一树脂基材12覆盖第一导体图案14和第二导体图案24，并且被接合到第二电路板20的第二树脂基材22，从而将第一电路板10和第二电路板20彼此连接。