公开(公告)号：US20010012692A1

公开(公告)日：2001-08-09

申请号：US09204405

申请日：1998-12-02

Inventor： ROBIN L. MILLER ,  PHUNG DAC NGUYEN

IPC: H01L021/44 ,  H01L021/302 ,  H01L021/461

CPC classification number: H05K3/26 ,  H05K1/092 ,  H05K3/06 ,  H05K3/064 ,  H05K3/1216 ,  H05K3/4685 ,  H05K2201/0761 ,  H05K2203/1476

Abstract: A method for making thick-film conductor line patterns having conductor linewidths and spacings which are each less than about 5 mils. The method is especially useful in manufacturing fine-line hybrid circuits. The method involves forming a conductor line circuit pattern of thick-film material on a principle surface of a substrate. The principle surface of the substrate is masked so that selected portions of the conductor line circuit pattern are exposed. The exposed portions of the pattern are then removed from the substrate to reduce the conductor linewidths and spacings of the pattern to less than about 5 mils.

Abstract translation: 一种用于制造具有导体线宽和间距的厚膜导体线图案的方法，它们都小于约5密耳。 该方法在制造细线混合电路中特别有用。 该方法包括在基板的主表面上形成厚膜材料的导线电路图案。 掩模基板的主表面，使导电线电路图案的选定部分露出。 然后从衬底去除图案的暴露部分，以将图案的导体线宽和间距减小到小于约5密耳。

公开(公告)号：US06221269B1

公开(公告)日：2001-04-24

申请号：US09233384

申请日：1999-01-19

Applicant: Krishna G. Sachdev ,  Umar M. Ahmad ,  Hsing H. Chen ,  Lawrence D. David ,  Charles H. Perry ,  Donald R. Wall

Inventor： Krishna G. Sachdev ,  Umar M. Ahmad ,  Hsing H. Chen ,  Lawrence D. David ,  Charles H. Perry ,  Donald R. Wall

IPC: C03C1500

CPC classification number: C04B41/009 ,  C04B41/5353 ,  C04B2111/00844 ,  H05K1/092 ,  H05K3/067 ,  H05K3/26 ,  H05K2201/0761 ,  H05K2203/0789

Abstract: A method is provided for etching and removing extraneous molybdenum or debris on ceramic substrates such as semiconductor devices and also for molybdenum etching in the fabrication of molybdenum photomasks. The method employs a multi-step process using an acidic aqueous solution of a ferric salt to remove (etch) the molybdenum debris followed by contacting the treated substrate with an organic quaternary ammonium hydroxide to remove any molybdenum black oxides which may have formed on the exposed surface of treated molybdenum features in ceramic substrates. The method is environmentally safe and the waste solutions may be easily waste treated for example by precipitating the ferric salts as ferric hydroxide and removing anions such as sulfate by precipitation with lime. The method replaces the currently used method of employing ferricyanide salts which create serious hazardous waste disposal and environmental problems.

Abstract translation: 提供了一种用于在陶瓷衬底（例如半导体器件）上蚀刻和去除外来的钼或碎片以及在钼光掩模的制造中用于钼蚀刻的方法。 该方法采用多步法，使用酸式的铁盐水溶液去除（蚀刻）钼碎片，随后将经处理的底物与有机季铵氢氧化物接触以除去可能形成于暴露的钼黑氧化物 处理的钼特征在陶瓷衬底中的表面。 该方法是环境安全的，并且废溶液可以容易地被废物处理，例如通过将铁盐沉淀为氢氧化铁并通过用石灰沉淀除去诸如硫酸盐的阴离子。 该方法取代了目前使用的铁氰化物盐的方法，造成严重的危险废物处理和环境问题。

公开(公告)号：US5302492A

公开(公告)日：1994-04-12

申请号：US067396

申请日：1993-05-24

Applicant: Albert Ott ,  Werner Motz ,  Werner Kornmayer ,  Michael Moser

Inventor： Albert Ott ,  Werner Motz ,  Werner Kornmayer ,  Michael Moser

IPC: H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  G03F7/36 ,  B05D3/00

CPC classification number: H05K3/427 ,  H05K3/108 ,  H05K3/24 ,  H05K3/244 ,  H05K2201/0347 ,  H05K2201/0761 ,  H05K2203/0361 ,  H05K2203/0571 ,  H05K2203/072 ,  H05K2203/0789 ,  H05K3/062 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4611

Abstract: A method of manufacturing printed circuit boards is disclosed wherein metallic conductive structures are produced in a desired pattern on a carrier board of isolating material. The method begins with the provision of a carrier board having a metal foil laminated to its surface and thereafter forming conductive traces on the carrier board, deactivating the carrier board to remove substantially all substances deposited on the carrier board other than the conductive traces and forming final conductive structures by electroless chemical metal deposition on the pattern of conductive traces. Circuit boards manufactured in accordance with such a method will have final conductor structures with base layer portions of the original laminated metal foil. In a preferred embodiment, the step of deactivating the carrier board involves rinsing the carrier board with hydrochloric acid. The method can be used for manufacturing single-layer or multilayer printed circuit boards with or without through-holes and permits the formation of conductor structures in the range of 50 micrometers or less.

Abstract translation: 公开了制造印刷电路板的方法，其中金属导电结构以期望的图案在隔离材料的载体板上制造。 该方法开始于提供具有层压到其表面上的金属箔的载体板，然后在载体板上形成导电迹线，使载体板去激活以除去沉积在除了导电迹线之外的载体板上的所有物质并形成最终 通过无电化学金属沉积在导电迹线图案上的导电结构。 根据这种方法制造的电路板将具有最初的导体结构，其中原始层压金属箔的基层部分。 在优选的实施方案中，使载体板失活的步骤包括用盐酸冲洗载体板。 该方法可以用于制造具有或不具有通孔的单层或多层印刷电路板，并且允许在50微米或更小的范围内形成导体结构。

公开(公告)号：US5221418A

公开(公告)日：1993-06-22

申请号：US833928

申请日：1992-02-11

Applicant: John L. Cordani

Inventor： John L. Cordani

IPC: B29C71/00 ,  H05K3/06 ,  H05K3/26

CPC classification number: H05K3/26 ,  B29C71/0009 ,  H05K2201/0761 ,  H05K2203/0783 ,  H05K2203/0793 ,  H05K3/06

Abstract: After the etching away of copper to selectively expose surface areas of insulating resin material in a printed circuit process based upon metal-clad insulating substrate material, the exposed surface areas of insulating material are contacted with a liquid treatment composition effective to soften or swell the resin material such that residual metal species otherwise associated with the surface area are removed or, at the least, become entrapped or encapsulated below a surface of resin, such that the surface insulation resistance afforded by the insulating surface areas of the printed circuit is improved.

Abstract translation: 在基于金属包覆的绝缘基板材料的印刷电路工艺中，在蚀刻掉铜以选择性地暴露绝缘树脂材料的表面积之后，绝缘材料的暴露表面积与有效地软化或溶胀树脂的液体处理组合物接触 使得除去与表面积相关的残余金属物质，或者至少被包埋或封装在树脂表面下方，从而提高了由印刷电路的绝缘表面积提供的表面绝缘电阻。

公开(公告)号：US4718972A

公开(公告)日：1988-01-12

申请号：US822216

申请日：1986-01-24

Applicant: Suryadevara V. Babu ,  William F. Herrmann ,  Joseph G. Hoffarth ,  Voya Markovich ,  Robert T. Wiley

Inventor： Suryadevara V. Babu ,  William F. Herrmann ,  Joseph G. Hoffarth ,  Voya Markovich ,  Robert T. Wiley

IPC: C23C18/30 ,  C23C18/36 ,  H05K3/08 ,  H05K3/18 ,  H05K3/26 ,  B05D3/04 ,  H05K3/22

CPC classification number: H05K3/08 ,  H05K3/184 ,  H05K3/26 ,  H05K2201/0761 ,  H05K2203/0783 ,  H05K2203/095 ,  H05K2203/1407

Abstract: A method of making a printed circuit board is disclosed wherein metallic seed particles are applied to a surface of the substrate. An image of the desired conductor pattern is defined by a maskant layer to permit the subsequent electroless deposition of the conductor material upon the exposed seeded areas of the substrate. Then, the substrate surface is subjected to a plasma discharge to facilitate removal of the seed particles.

Abstract translation: 公开了制造印刷电路板的方法，其中将金属种子颗粒施加到基底的表面。 所需导体图案的图像由掩模层限定，以允许导体材料随后无电沉积在衬底的暴露的种子区域上。 然后，对衬底表面进行等离子体放电以便于除去种子颗粒。

公开(公告)号：US20240224409A1

公开(公告)日：2024-07-04

申请号：US18420769

申请日：2024-01-24

Applicant: FUJIFILM Corporation

Inventor： Yusuke FUJII

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0216 ,  H05K1/0215 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2203/013 ,  H05K2203/1377

Abstract: Provided are an electronic device including: a wiring board having a mounting surface; a ground electrode that defines a ground region on the mounting surface; an electronic component that is located on the mounting surface and is disposed in the ground region; a conductive component that is disposed adjacent to an outer edge of the ground electrode; an internal insulating protective layer that is disposed in the ground region and covers the electronic component; an external insulating protective layer that is disposed outside the ground region and covers the conductive component; and an electromagnetic wave shielding layer that is provided to extend over the internal insulating protective layer and the ground electrode and that covers the internal insulating protective layer and is electrically connected to the ground electrode, the electromagnetic wave shielding layer being a solidified product of an ink for forming an electromagnetic wave shielding layer, and a manufacturing method thereof.

公开(公告)号：US11792919B2

公开(公告)日：2023-10-17

申请号：US17427954

申请日：2020-03-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Lee Francis

IPC: H05K1/02 ,  H05K1/18 ,  H05K7/14

CPC classification number: H05K1/0256 ,  H05K1/181 ,  H05K7/1427 ,  H05K2201/0761 ,  H05K2201/09063 ,  H05K2201/09972 ,  H05K2201/1003

Abstract: A case includes a header with a first isolation barrier, a cover with a second isolation barrier, and a printed circuit board (PCB) including a slot in which the first isolation barrier or the second isolation barrier is located and a primary-circuit side and a secondary-circuit side located on opposites sides of the slot.

公开(公告)号：US20180249572A1

公开(公告)日：2018-08-30

申请号：US15841448

申请日：2017-12-14

Applicant: ASIA ELECTRONIC MATERIAL CO., LTD.

Inventor： Wei-Chih Lee ,  Li-Chih Yang ,  Chien-Hui Lee

IPC: H05K1/02 ,  H05K3/28

CPC classification number: H05K1/024 ,  B32B27/08 ,  B32B27/32 ,  B32B2255/10 ,  B32B2255/26 ,  B32B2457/08 ,  H05K1/0274 ,  H05K3/28 ,  H05K3/281 ,  H05K2201/012 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0761 ,  H05K2203/066 ,  H05K2203/161

Abstract: A colored thin covering film is provided, including an upper detached layer, a colored ink film, a low dielectric glue layer, and a lower detached layer. The color ink layer is formed between the upper detached layer and the low dielectric glue layer. The low dielectric glue layer is formed between the colored ink layer and the lower detached layer. The thickness of the colored ink layer is between 1 to 10 μm, and the thickness of the low dielectric glue layer is between 3 to 25 μm, such that a total thickness of the colored ink layer and the low dielectric glue layer is allowed to be between 4 to 35 μm. The colored thin covering film has an extremely low dielectric constant and loss, extremely low ion migration, good adhesion, heat dissipation, high flexibility, and low resilience, and can be processed in a low temperature.

公开(公告)号：US09532468B2

公开(公告)日：2016-12-27

申请号：US14549951

申请日：2014-11-21

Applicant: IBIDEN Co., Ltd.

Inventor： Masatoshi Kunieda ,  Makoto Terui ,  Ryoujiro Tominaga ,  Takashi Kariya

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H05K3/24 ,  H05K3/34

CPC classification number: H05K3/4682 ,  H01L2224/16227 ,  H05K1/0256 ,  H05K1/0265 ,  H05K1/09 ,  H05K1/112 ,  H05K1/113 ,  H05K1/114 ,  H05K1/185 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/0989 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/1394 ,  Y02P70/611 ,  Y10T29/49155

Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.

Abstract translation: 布线基板包括第一树脂绝缘层，第一绝缘层上包括第一和第二导体焊盘的导体焊盘，覆盖第一和第二焊盘的第一绝缘层上的第二树脂绝缘层，第二绝缘层上的最外层导体层 包括第一和第二最外面布线层，通过第二绝缘层的通孔导体包括连接第一布线层和第一焊盘的第一通孔导体和连接第二布线层和第二焊盘的第二通孔导体，以及在第二绝缘层上的阻焊层 绝缘层，使得阻焊层覆盖第一布线层并且具有暴露第二布线层的一个或多个开口。 第一布线层包括第一主金属，第二布线层包括与第一布线层的第一金属不同的第二主金属。

公开(公告)号：US20160198562A1

公开(公告)日：2016-07-07

申请号：US14916606

申请日：2014-09-19

Applicant: Michael BRUBAKER ,  Terry HOSKING ,  SBE INC.

Inventor： Michael Brubaker ,  Terry Hosking

IPC: H05K1/02 ,  H01B17/56 ,  H01B17/00

CPC classification number: H05K1/0256 ,  H01B17/005 ,  H01B17/56 ,  H01L25/07 ,  H01L2924/0002 ,  H02M7/003 ,  H05K2201/0746 ,  H05K2201/0761 ,  H05K2201/10053 ,  H01L2924/00

Abstract: Semiconductor switch modules have positive and negative electrical input connections which must be spaced adequately to prevent a short circuit flashover between the polarities. This terminal spacing is defined by the strike distance through air or creepage distance through air along an insulating surface between the two input connections given the operating voltage per regulatory agency requirements. The inductance of the switch connections is ultimately limited by this terminal spacing. A novel conformal solid insulation scheme between the bus structure and switch module eliminates the strike or creepage paths through air and allows for reduced terminal spacing and lower inductance while meeting regulatory agency requirements.

Abstract translation: 半导体开关模块具有正和负电输入连接，其必须充分间隔以防止极性之间的短路闪络。 这个端子间距由给定每个管理机构要求的工作电压的两个输入连接之间通过空气的打击距离或沿着绝缘表面的空气的爬电距离来定义。 开关连接的电感最终受到端子间距的限制。 总线结构和开关模块之间的一种新颖的保形固体绝缘方案消除了通过空气的罢工或爬电路径，并允许减小端子间距和降低电感，同时满足管理机构的要求。