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    MULTILAYER SUBSTRATE MODULE
    81.
    发明申请
    MULTILAYER SUBSTRATE MODULE 有权
    多层基板模块

    公开(公告)号：US20140202750A1

    公开(公告)日：2014-07-24

    申请号：US14148979

    申请日：2014-01-07

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Takeshi KOGURE ,  Hiromichi KITAJIMA

    IPC: H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/165 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/0969

    Abstract: A multilayer substrate module includes a multilayer circuit substrate, a mounting land, and an input/output terminal. Inside the multilayer circuit substrate, a wiring line that connects the mounting land and the input/output terminal to each other, an inductor that defines a portion of the wiring line, a first ground conductor that is positioned on the one main surface side of the inductor, and a second ground conductor that is positioned on the other main surface side of the inductor are defined by conductor patterns. The area where inductor is located is not superposed with the area where the second ground conductor is located, when the one main surface or the other main surface of the multilayer circuit substrate is viewed in plan, the second ground conductor being closer to the layer where the inductor is located than the first ground conductor is.

    Abstract translation: 多层基板模块包括多层电路基板，安装台面和输入/输出端子。 在多层电路基板的内部，将安装台面和输入输出端子彼此连接的布线，限定布线的一部分的电感器，位于第一接地导体的一个主面侧的第一接地导体 电感器和位于电感器的另一主表面侧的第二接地导体由导体图案限定。 电感器所在的区域不与第二接地导体所在的区域重叠，当在平面图中观察多层电路衬底的一个主表面或另一个主表面时，第二接地导体更靠近层 电感器位于第一接地导体之上。

    CIRCUITRY ARRANGEMENT FOR REDUCING A TENDENCY TOWARDS OSCILLATIONS
    82.
    发明申请
    CIRCUITRY ARRANGEMENT FOR REDUCING A TENDENCY TOWARDS OSCILLATIONS 有权
    电路安排减少扭转的趋势

    公开(公告)号：US20140192487A1

    公开(公告)日：2014-07-10

    申请号：US14210697

    申请日：2014-03-14

    Applicant: SMA Solar Technology AG

    Inventor： Regine Mallwitz

    IPC: H05K1/18

    CPC classification number: H05K1/181 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/3011 ,  H02M7/003 ,  H05K1/0228 ,  H05K1/0234 ,  H05K1/0263 ,  H05K1/165 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/083 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A circuitry arrangement includes several electronic parts mounted to a circuit board, at least one conductor section extending between the electronic parts within a first conductor layer, and a closed conductor loop comprising at least one loop section running in parallel to the at least one conductor section within a second conductor layer neighboring the first conductor layer. The closed conductor loop is configured to reduce a tendency towards oscillations of a current flowing through the conductor section in operation of the circuitry arrangement. The conductor loop is closed via at least one electronic component mounted to an outer surface of the circuit board.

    Abstract translation: 电路装置包括安装到电路板的多个电子部件，在第一导体层内的电子部件之间延伸的至少一个导体部分和闭合导体回路，该闭合导体回路包括至少一个与至少一个导体部分平行运行的回路部分 在与第一导体层相邻的第二导体层内。 闭合导体环路被配置为在电路装置的操作中减小流过导体部分的电流的振荡趋势。 通过安装到电路板的外表面的至少一个电子部件来闭合导体环路。

    Substrate device with a transmission line connected to a connector pad and method of manufacture
    83.
    发明授权
    Substrate device with a transmission line connected to a connector pad and method of manufacture 有权
    具有连接到连接器焊盘的传输线的基板装置和制造方法

    公开(公告)号：US08258888B2

    公开(公告)日：2012-09-04

    申请号：US12588731

    申请日：2009-10-26

    Applicant: Hidetaka Ootsuka

    Inventor： Hidetaka Ootsuka

    IPC: H01P5/02

    CPC classification number: H05K1/117 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/025 ,  H05K2201/0792 ,  H05K2201/09663 ,  H05K2201/09909 ,  H05K2201/10318 ,  Y10T29/49204

    Abstract: A substrate device includes: a substrate; a ground layer disposed on one of two opposing surfaces of the substrate; a transmission line disposed on the other of the two opposing surfaces of the substrate; a pad which is disposed on the other of the two opposing surfaces of the substrate and connected to the transmission line; and a connector connected to the pad via a contact point. The pad has a part on the transmission line side and a part positioned on the opposite side of the transmission line with respect to the contact point with the connector which are electrically insulated from each other.

    Abstract translation: 衬底装置包括：衬底; 设置在所述基板的两个相对表面中的一个上的接地层; 布置在所述基板的所述两个相对表面中的另一个表面上的传输线; 衬垫，其设置在所述衬底的所述两个相对表面中的另一个上并连接到所述传输线; 以及通过接触点连接到焊盘的连接器。 衬垫在传输线侧具有一部分，并且相对于彼此电绝缘的与连接器的接触点位于传输线相对侧的部分。

    NON-CONTACT POWER RECEIVING APPARATUS
    84.
    发明申请
    NON-CONTACT POWER RECEIVING APPARATUS 有权
    非接触式电力接收装置

    公开(公告)号：US20110278951A1

    公开(公告)日：2011-11-17

    申请号：US13194383

    申请日：2011-07-29

    Applicant: Takeshi KURIHARA ,  Keiichi ICHIKAWA

    Inventor： Takeshi KURIHARA ,  Keiichi ICHIKAWA

    IPC: H01F38/14

    CPC classification number: H02J50/10 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H02J50/70 ,  H05K1/0216 ,  H05K1/0265 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/09627 ,  H05K2201/097 ,  H05K2201/0979 ,  H05K2201/1003 ,  H05K2201/10166

    Abstract: The disclosure provides a non-contact power receiving apparatus including a conductive pattern in a second region of a substrate not covered by a magnetic sheet. The conductive pattern includes first and second electrodes provided in a first plane parallel to a surface of the substrate and arranged in a length direction of the conductive pattern. A third electrode is formed on a second plane parallel with the first plane. A first via hole connects superposed portions of the first and third electrodes to each other, and a second via hole connects superposed portions of the second and third electrodes to each other. As a result, loops of eddy currents generated in the conductive pattern can be made to be small, whereby eddy current loss can be reduced.

    Abstract translation: 本公开提供一种非接触式电力接收装置，其包括在未被磁性片覆盖的基板的第二区域中的导电图案。 导电图案包括设置在与基板的表面平行的第一平面中并沿导电图案的长度方向布置的第一和第二电极。 第三电极形成在与第一平面平行的第二平面上。 第一通孔将第一和第三电极的叠置部彼此连接，第二通孔将第二电极和第三电极的叠置部彼此连接。 结果，可以使在导电图案中产生的涡流的回路小，从而可以减小涡流损耗。

    METHOD OF IMPROVING ISOLATION BETWEEN CIRCUITS ON A PRINTED CIRCUIT BOARD
    85.
    发明申请
    METHOD OF IMPROVING ISOLATION BETWEEN CIRCUITS ON A PRINTED CIRCUIT BOARD 有权
    改善打印电路板上电路间隔离的方法

    公开(公告)号：US20100291795A1

    公开(公告)日：2010-11-18

    申请号：US12467185

    申请日：2009-05-15

    Applicant: Adam W. Gibson ,  Jeffrey Alan Poulsen

    Inventor： Adam W. Gibson ,  Jeffrey Alan Poulsen

    IPC: H01R24/00 ,  H04B3/28 ,  H05K1/03

    CPC classification number: H05K1/0225 ,  H05K1/0216 ,  H05K1/0228 ,  H05K1/024 ,  H05K3/0044 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/10189 ,  Y10T29/49124

    Abstract: A method of improving electrical isolation between a first circuit and a second circuit sharing a common substrate having an effective dielectric constant greater than that of air. The first and second circuits are spaced apart and separated from one another by an intermediate portion of the substrate. The method includes removing a portion of the intermediate portion to replace the portion removed with air thereby reducing the effective dielectric constant of the intermediate portion. By reducing the effective dielectric constant of the intermediate portion, electrical isolation between the first and second circuits is improved thereby reducing crosstalk between the first and second circuits. In particular implementations, the method may be used to reduce alien crosstalk between adjacent communication outlets in a patch panel.

    Abstract translation: 一种改善第一电路和共享具有大于空气的有效介电常数的公共衬底的第二电路之间的电隔离的方法。 第一和第二电路间隔开并且通过衬底的中间部分彼此分离。 该方法包括去除中间部分的一部分以取代用空气除去的部分，从而降低中间部分的有效介电常数。 通过降低中间部分的有效介电常数，改善第一和第二电路之间的电隔离，从而减少第一和第二电路之间的串扰。 在具体的实现中，该方法可以用于减少接线板中的相邻通信插座之间的外来串扰。

    APPARATUS AND METHOD OF VIA-STUB RESONANCE EXTINCTION
    87.
    发明申请
    APPARATUS AND METHOD OF VIA-STUB RESONANCE EXTINCTION 审中-公开
    装置和方法进行共振共振放电

    公开(公告)号：US20090295498A1

    公开(公告)日：2009-12-03

    申请号：US12543854

    申请日：2009-08-19

    Applicant: Lei Shan ,  Jeannine Trewhella

    Inventor： Lei Shan ,  Jeannine Trewhella

    IPC: H01P5/02

    CPC classification number: H05K1/023 ,  H05K1/0246 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/10022 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

    Abstract: An apparatus includes a multi-layer printed circuit board having a first through-hole via for a signal connection and a second through hole via for power/ground connections. The printed circuit includes a transmission line connected to at least one through-hole via. A resistor is connected between the first and second through-hole vias to eliminate a resonance notch and achieve a flat frequency response for insertion loss.

    Abstract translation: 一种装置包括具有用于信号连接的第一通孔通孔和用于电力/接地连接的第二通孔通孔的多层印刷电路板。 印刷电路包括连接到至少一个通孔通孔的传输线。 电阻器连接在第一通孔和第二通孔之间以消除谐振陷波并实现用于插入损耗的平坦频率响应。

    DUAL DENSITY PRINTED CIRCUIT BOARD ISOLATION PLANES AND METHOD OF MANUFACTURE THEREOF
    89.
    发明申请
    DUAL DENSITY PRINTED CIRCUIT BOARD ISOLATION PLANES AND METHOD OF MANUFACTURE THEREOF 审中-公开
    双密度印刷电路板隔离板及其制造方法

    公开(公告)号：US20090173524A1

    公开(公告)日：2009-07-09

    申请号：US11970360

    申请日：2008-01-07

    Applicant: Chad W. Morgan

    Inventor： Chad W. Morgan

    IPC: H05K1/09 ,  H05K1/00 ,  H05K3/00

    CPC classification number: H05K3/4623 ,  H05K1/0218 ,  H05K1/0253 ,  H05K1/18 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2203/1572 ,  Y10T29/49124

    Abstract: A conductive power isolation plane for reducing interlayer cross-talk in a printed circuit board between conductive through vias on one side of the printed circuit board and conductive through vias on the other side of the printed circuit board and a method of manufacturing the same. In one embodiment, a printed circuit board includes a (1) conductive power isolation plane interlaminated within a plurality of insulating dielectric layers, (2) a first dielectric layer having a conductive through via laminated to a surface of the plurality of insulating dielectric layers, (3) a second dielectric layer having a conductive through via laminated to a surface of the plurality of insulating dielectric layers opposite the first dielectric layer and (4) a conductive ground via extending through the first dielectric layer, the plurality of insulating layers, including the conductive power isolation plane, and the second dielectric layer.

    Abstract translation: 一种导电功率隔离平面，用于在印刷电路板的一侧上的导电通孔之间减少印刷电路板中的层间串扰，并且在印刷电路板的另一侧上通过导电孔，以及制造印刷电路板的方法。 在一个实施例中，印刷电路板包括层叠在多个绝缘电介质层内的（1）导电功率隔离面，（2）具有层压到多个绝缘介电层的表面的导电通孔的第一介电层， （3）第二电介质层，其具有层压到与所述第一电介质层相对的所述多个绝缘电介质层的表面的导电通孔，以及（4）延伸穿过所述第一介电层的导电接地，所述多个绝缘层包括 导电功率隔离面和第二介质层。

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