公开(公告)号：US20160066439A1

公开(公告)日：2016-03-03

申请号：US14784080

申请日：2014-04-03

Applicant: DENSO CORPORATION

Inventor： Hiroaki ANDO ,  Kiminobu INAYOSHI ,  Tetsuichi TAKEUCHI ,  Naoto MAKINO ,  Tetsuya SUEYOSHI ,  Kenichi KATOH ,  Keisuke NISHIO

IPC: H05K5/00 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K5/0013 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16013 ,  H01L2924/3512 ,  H05K1/0213 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09436 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/613

Abstract: A vehicular electronic device has a semiconductor package and a multilayer wiring board. An electrode pad of the multilayer wiring board, to which a signal terminal of the semiconductor package is soldered, has a wiring pattern in an inner layer of the multilayer wiring board. A solder resist is applied and spaced from a periphery of the electrode pad to the exterior. The signal terminal is soldered to the electrode pad to cover an upper surface and an upper end of a side surface of the electrode pad. As a result, a crack is less likely to occur in solder connected to the signal terminal. Therefore, the signal terminal can be electrically connected with high reliability even when the signal terminal is provided in the semiconductor package with a small number.

Abstract translation: 车载电子设备具有半导体封装和多层布线板。 多层布线基板的电极焊盘，其上焊接有半导体封装的信号端子，在多层布线基板的内层具有布线图形。 施加阻焊剂并与电极垫的外围间隔开至外部。 信号端子被焊接到电极焊盘以覆盖电极焊盘的侧表面的上表面和上端。 结果，在与信号端子连接的焊料中不太可能发生裂纹。 因此，即使信号端子以少数提供在半导体封装中，信号端子也可以高可靠性地电连接。

公开(公告)号：US20160062172A1

公开(公告)日：2016-03-03

申请号：US14678406

申请日：2015-04-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Chong-Guk Lee ,  Joo-Yeon Won ,  Se-Hui Jang ,  Su-Mi Moon ,  Dong-Wook Lee

IPC: G02F1/1345 ,  H01L23/00 ,  H01L27/12

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate, The IC Chip is electrically connected to the input line. The output line includes a main output and a sub output line, The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

Abstract translation: 薄膜封装芯片包括基底基板，输入线，集成电路（IC）芯片和输出线。 输入线设置在基底基板上.IC芯片电连接到输入线。 输出线包括主输出和副输出线。主输出线与IC芯片电连接，并从IC芯片沿第一方向延伸。 副输出线电连接到IC芯片。 子输出线包括至少六个弯曲部分，并且沿第一方向延伸。

公开(公告)号：US09269688B2

公开(公告)日：2016-02-23

申请号：US14072896

申请日：2013-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16013 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/3003 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/3841 ,  H05K1/111 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

Abstract translation: 包装包括第一和第二包装组件。 第一包装部件包括在第一包装部件的表面处的第一金属痕迹和第二金属迹线。 第二金属迹线与第一金属迹线平行。 第二金属迹线包括具有第一宽度的窄金属迹线部分和具有大于连接到窄金属迹线部分的第一宽度的第二宽度的宽金属迹线部分。 第二个包组件超过了第一个包组件。 第二封装部件包括与第一金属迹线的一部分重叠的金属凸块和将金属凸块接合到第一金属迹线的导电连接。 导电连接接触第一金属轨迹的顶表面和侧壁。 金属凸块与窄金属迹线部分相邻。

公开(公告)号：US09252138B2

公开(公告)日：2016-02-02

申请号：US14287237

申请日：2014-05-27

Applicant: General Electric Company

Inventor： Gamal Refai-Ahmed ,  David Mulford Shaddock ,  Arun Virupaksha Gowda ,  John Anthony Vogel ,  Christian Giovanniello

IPC: H01L33/02 ,  H01L25/16 ,  H01L25/00 ,  H01L33/62 ,  H01L33/64 ,  H01L33/54 ,  H01S5/022 ,  H01S5/024 ,  H01L23/538

CPC classification number: H01L23/5386 ,  H01L23/49811 ,  H01L33/62 ,  H01L2924/0002 ,  H01S5/02256 ,  H05K3/32 ,  H05K2201/0311 ,  H05K2201/10674 ,  H01L2924/00

Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.

Abstract translation: 提供一种具有半导体集成电路和多个互连部件的电子封装组件。 多个互连部件可操作地耦合到半导体集成电路。 此外，一个或多个互连部件包括具有第一表面和第二表面的一个或多个支撑元件，以及具有第一端和第二端的一个或多个弹簧元件，并且其中一个或多个弹簧元件的第一端连接 到相应的支撑元件的第一表面或第二表面。

公开(公告)号：US09252066B2

公开(公告)日：2016-02-02

申请号：US13207633

申请日：2011-08-11

Applicant: Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US20160029494A1

公开(公告)日：2016-01-28

申请号：US14871622

申请日：2015-09-30

Applicant: Shinkawa Ltd.

Inventor： Koji HOJO ,  Makoto TAKAHASHI

IPC: H05K3/34

CPC classification number: H05K3/3494 ,  H01L21/67011 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/1601 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75305 ,  H01L2224/75502 ,  H01L2224/75744 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/75901 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12043 ,  H05K3/3436 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic component mounting apparatus includes a bonding tool for thermally bonding an electronic component onto a substrate, the bonding tool to be driven in a direction getting close to and from the substrate, a linear scale and a linear scale head detecting the position of the bonding tool in the direction getting close to and from the substrate, and a control unit configured to hold the position of the bonding tool in the direction getting close to and from the substrate when a solder film between an electrode of the electronic component and an electrode of the substrate is thermally fused when the bonding tool gets close to the substrate by a predetermined distance from a reference position while heating the electronic component. The electronic component mounting apparatus for bonding the electronic component and the substrate with thermally fusible bond metal offers an improvement in the bonding quality.

公开(公告)号：US20160021743A1

公开(公告)日：2016-01-21

申请号：US14583317

申请日：2014-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/40 ,  H05K1/02 ,  H05K3/02

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US09240380B2

公开(公告)日：2016-01-19

申请号：US13715424

申请日：2012-12-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00 ,  H05K1/18 ,  H05K3/00 ,  H01L25/03 ,  H01L25/065 ,  H01L25/16 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/27002 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/007 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

公开(公告)号：US20160014898A1

公开(公告)日：2016-01-14

申请号：US14798550

申请日：2015-07-14

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Wataru Nakamura ,  Tomoyoshi Hirabayashi

IPC: H05K1/14 ,  H05K1/09 ,  H01L23/498 ,  H05K1/18

CPC classification number: H05K1/144 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H05K1/09 ,  H05K1/185 ,  H05K3/4007 ,  H05K2201/0326 ,  H05K2201/0364 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/09372 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/0723

Abstract: A printed wiring board includes a first circuit substrate having first pads and second pads such that the first pads are positioned to mount an electronic component on the first circuit substrate and that the second pads are positioned to electrically connect the first circuit substrate to a second circuit substrate, and metal posts including plating material and formed on the second pads respectively such that the metal posts are positioned to mount the second circuit substrate on the first circuit substrate. Each of the metal posts has a height h1 and a thickness b such that the metal posts have a value h1/b which is greater than 0.1 and smaller than 1.0 where the value h1/b is obtained by dividing the height h1 by the thickness b.

Abstract translation: 印刷布线板包括具有第一焊盘和第二焊盘的第一电路基板，使得第一焊盘被定位成将电子部件安装在第一电路基板上，并且第二焊盘被定位成将第一电路基板电连接到第二电路 基板和包括电镀材料的金属柱并分别形成在第二焊盘上，使得金属柱被定位成将第二电路基板安装在第一电路基板上。 每个金属柱具有高度h1和厚度b，使得金属柱具有大于0.1且小于1.0的值h1 / b，其中通过将高度h1除以厚度b获得值h1 / b 。

公开(公告)号：US20160013123A1

公开(公告)日：2016-01-14

申请号：US14562972

申请日：2014-12-08

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/11 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H05K1/111 ,  H05K3/4697 ,  H05K2201/10674

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠电介质层; 在所述电介质层中形成多个导电柱; 以及在所述电介质层中形成空腔以暴露所述接合焊盘，其中所述导电柱围绕所述空腔的周边定位，由此简化所述制造工艺。