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公开(公告)号:JPS62105445A
公开(公告)日:1987-05-15
申请号:JP19300486
申请日:1986-08-20
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , SILVESTRI VICTOR JOSEPH
IPC: H01L21/76 , H01L21/225 , H01L21/74 , H01L21/763 , H01L29/41
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公开(公告)号:JPS62101034A
公开(公告)日:1987-05-11
申请号:JP19302286
申请日:1986-08-20
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , MAKRIS JAMES STEVE , MENDEL ERIC , NUMMY KAREN ANN , OGURA SEIKI , RISEMAN JACOB , ROVEDO NIVO
IPC: H01L21/76 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/3105 , H01L21/74 , H01L21/762 , H01L21/763
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公开(公告)号:DE3686125T2
公开(公告)日:1993-03-11
申请号:DE3686125
申请日:1986-10-10
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , SILVESTRI VICTOR JOSEPH
IPC: H01L21/76 , H01L21/225 , H01L21/74 , H01L21/763 , H01L29/41 , H01L21/20
Abstract: A method of simultaneously producing doped silicon filled trenches (20) in areas where a substrate contact is to be produced and trench isolation (18) in other areas. Borosilicate glass (28) lines the sidewalls of those trenches (20) where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate (28) to dope the epitaxial silicon in those trenches. In the other trenches (18), the silicon fill remains undoped except at the bottom where a channel stop (32) exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.
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公开(公告)号:DE3676458D1
公开(公告)日:1991-02-07
申请号:DE3676458
申请日:1986-07-29
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , GUTHRIE WILLIAM LESLIE , MARKAREWICZ STANLEY RICHARD , MENDEL ERIC , PATRICK WILLIAM JOHN , PERRY KATHLEEN ALICE , PLISKIN WILLIAM AARON , RISEMAN JACOB , SCHIABLE PAUL MARTIN , STANDLEY CHARLES LAMBER
IPC: H01L21/3205 , H01L21/304 , H01L21/3105 , H01L21/3213 , H01L21/768 , H01L21/306 , H01L21/60
Abstract: A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate (31) having a patterned insulating layer (32) of dielectric material thereon, is coated with a layer of metal (34). The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes (33) where it is left intact (34a). This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier.
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公开(公告)号:DE3850843T2
公开(公告)日:1995-03-09
申请号:DE3850843
申请日:1988-09-13
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , LU-CHEN HSU LOUIS , SCHEPIS DOMINIC JOSEPH , SILVESTRI VICTOR JOSEPH
IPC: H01L21/205 , H01L21/76 , H01L21/762 , H01L21/20
Abstract: A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.
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公开(公告)号:DE2728985A1
公开(公告)日:1978-01-05
申请号:DE2728985
申请日:1977-06-28
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , DAS GOBINDA , POPONIAK MICHAEL ROBERT , YEH TSU-HSING
IPC: H01L29/73 , H01L21/265 , H01L21/28 , H01L21/322 , H01L21/331 , H01L29/32
Abstract: A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.
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公开(公告)号:DE3584739D1
公开(公告)日:1992-01-09
申请号:DE3584739
申请日:1985-05-10
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , SILVESTRI VICTOR JOSEPH
IPC: H01L21/76 , H01L21/20 , H01L21/74 , H01L21/763
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公开(公告)号:DE3681696D1
公开(公告)日:1991-10-31
申请号:DE3681696
申请日:1986-07-29
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , MAKRIS JAMES STEVE , MENDEL ERIC , NUMMY KAREN ANN , OGURA SEIKI , RISEMAN JACOB , ROVEDO NIVO
IPC: H01L21/76 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/3105 , H01L21/74 , H01L21/762 , H01L21/763
Abstract: A chemical-mechanical (chem-mech) method for removing SiO₂ protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si₃N₄ (29) is deposited onto the wafer surface, which is then chem-mech polished with a SiO₂ water based slurry. The Si₃N₄ acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si₃N₄ layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO₂ protuberances are removed to provide a substantially planar integrated structure.
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公开(公告)号:DE3279277D1
公开(公告)日:1989-01-12
申请号:DE3279277
申请日:1982-03-09
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , LOGAN JOSEPH SKINNER
IPC: H01L29/73 , H01L21/033 , H01L21/205 , H01L21/265 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/331 , H01L21/76 , H01L21/762 , H01L29/732
Abstract: There is provided a process for manufacturing high density integrated circuits where transistor emitter-base isolation distances are established with high precision and, if there is any misalignment during photolithographic procedures, such misalignment occurs in a wide dielectric isolation without adverse impact on transistor performance. The process comprises: a) producing an ion-implantation resistant island on a substrate; b) growing ion-implantation resistant sidewalls on the island; c) implanting a first impurity; d) removing the sidewalls; e) implanting a second impurity where the sidewalls were; f) growing a conformal etchable coating over the surface of the device; g) masking to define an area spaced from and exterior to the area where the sidewalis were; h) removing the conformal etchable coating in the area of step g); i) etching a deep trench in the area where the conformal coating was removed; j) implanting a third impurity into the deep trench; k) filling said deep trench (47a, b) with a dielectric material. Following island removal, the emitter and base of a bipolar transistor are formed in the area where the island existed.
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公开(公告)号:DE3850843D1
公开(公告)日:1994-09-01
申请号:DE3850843
申请日:1988-09-13
Applicant: IBM
Inventor: BEYER KLAUS DIETRICH , LU-CHEN HSU LOUIS , SCHEPIS DOMINIC JOSEPH , SILVESTRI VICTOR JOSEPH
IPC: H01L21/205 , H01L21/76 , H01L21/762 , H01L21/20
Abstract: A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.
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