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    MULTIPLE MATERIAL STACKS WITH A STRESS RELIEF LAYER BETWEEN A METAL STRUCTURE AND A PASSIVATION LAYER AND METHOD
    2.
    发明申请
    MULTIPLE MATERIAL STACKS WITH A STRESS RELIEF LAYER BETWEEN A METAL STRUCTURE AND A PASSIVATION LAYER AND METHOD 审中-公开
    具有金属结构和钝化层之间的应力消除层的多个材料堆叠和方法

    公开(公告)号：WO02069368A3

    公开(公告)日：2002-11-21

    申请号：PCT/GB0200758

    申请日：2002-02-20

    Applicant: IBM ,  IBM UK

    Inventor： WANG PING-CHUAN ,  EDWARDS ROBERT DANIEL ,  MALINOWSKI JOHN ,  RAMACHANDRAN VIDHYA ,  KALDOR STEFFEN

    IPC: H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/64

    CPC classification number: H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/3192 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer. In particular, the dielectric passivation layer between the metallic structure and the low stress modulus buffer material has a thermal coefficient of expansion between about 5ppm/ DEG C and about 20ppm/ DEG C.

    Abstract translation: 一种用于减小电介质，钝化层和金属结构之间的应力的结构/方法，包括用低应力模量缓冲材料涂覆金属结构，以及形成覆盖低应力模量缓冲材料的电介质钝化层。 低应力模量缓冲材料由选自氢/烷烃SQ（SilsesQuioxane）树脂，聚酰亚胺和聚合物树脂中的至少一种的聚合材料层组成。 电介质钝化层由至少一层选自氧化硅和氮化硅中的至少一种的材料组成。 在电介质钝化层上形成保护层。 低应力模量缓冲材料具有在金属结构和介电钝化层的热膨胀系数之间的热膨胀系数。 特别地，金属结构和低应力模量缓冲材料之间的介电钝化层的热膨胀系数为约5ppm /℃至约20ppm /℃。

    5.
    发明专利
    未知

    公开(公告)号：AT470237T

    公开(公告)日：2010-06-15

    申请号：AT03796085

    申请日：2003-12-08

    Applicant: IBM

    Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

    IPC: H01L21/768

    Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

    Multiple material stacks with a stress relief layer between a metal structure and a passivation layer and method
    8.
    发明专利
    Multiple material stacks with a stress relief layer between a metal structure and a passivation layer and method 未知

    公开(公告)号：AU2002232005A1

    公开(公告)日：2002-09-12

    申请号：AU2002232005

    申请日：2002-02-20

    Applicant: IBM

    Inventor： WANG PING-CHUAN ,  RAMACHANDRAN VIDHYA ,  EDWARDS ROBERT DANIEL ,  MALINOWSKI JOHN ,  KALDOR STEFFEN

    IPC: H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/64

    Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer. In particular, the dielectric passivation layer between the metallic structure and the low stress modulus buffer material has a thermal coefficient of expansion between about 5 ppm/° C. and about 20 ppm/° C.

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