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    Method for forming germanium-on-insulator semiconductor structure using porous layer and semiconductor structure formed by the method
    2.
    发明专利
    Method for forming germanium-on-insulator semiconductor structure using porous layer and semiconductor structure formed by the method 审中-公开
    使用多孔膜形成的绝缘子半导体结构和半导体结构的方法

    公开(公告)号：JP2007123875A

    公开(公告)日：2007-05-17

    申请号：JP2006284413

    申请日：2006-10-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHENG KANGGUO ,  GREENE BRIAN J ,  MANDELMAN JACK ALLAN

    IPC: H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

    CPC classification number: H01L21/76251 ,  H01L21/76245 ,  Y10S438/933

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a germanium-on-insulator semiconductor structure using a porous layer, and a semiconductor structure formed by the method.
    SOLUTION: This semiconductor structure comprises a layer containing a single crystal germanium which is preferably substantially pure germanium, a substrate and an embedded insulating layer for separating the layer containing germanium from the substrate. A porous layer which can be converted into a porous silicone layer is formed on the substrate and the layer containing germanium is formed on the porous silicone layer. By converting the porous layer into an oxide layer, an embedded insulating layer can be formed. Alternatively, the layer containing germanium on the porous layer can be moved to an insulating layer on another substrate. After moved, an insulating layer is embedded between the later substrate and the layer containing germanium.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种使用多孔层形成绝缘体上的锗锗的方法，以及通过该方法形成的半导体结构。 解决方案：该半导体结构包括含有优选基本上纯锗的单晶锗的层，用于将含锗层与基板分离的衬底和嵌入绝缘层的层。 在基材上形成能够转化为多孔硅酮层的多孔层，在多孔硅树脂层上形成含锗层。 通过将多孔层转化为氧化物层，可以形成嵌入绝缘层。 或者，可以在多孔层上含有锗的层移动到另一基底上的绝缘层。 移动后，在后面的基板和含有锗的层之间嵌入绝缘层。 版权所有（C）2007，JPO＆INPIT

    FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF
    3.
    发明专利
    FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH11251579A

    公开(公告)日：1999-09-17

    申请号：JP507999

    申请日：1999-01-12

    Applicant: IBM

    Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

    IPC: H01L29/78 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor having a substantially isolated body. SOLUTION: This field-effect transistor as an insulated gate field-effect transistor 10 has a device region 17, formed on a semiconductor material-made substantially electrically isolated region contact a semiconductor substrate 16 via a neck region 13 capable of exchanging charged carriers with the semiconductor substrate 16. The device region 17 of the transistor 10 is isolated from the electric contact to the substrate 16 at a surface other than that of the neck region 13.

    SUBMINIMUM WIRING STRUCTURE
    5.
    发明专利
    SUBMINIMUM WIRING STRUCTURE 失效

    公开(公告)号：JP2000036566A

    公开(公告)日：2000-02-02

    申请号：JP14867499

    申请日：1999-05-27

    Applicant: IBM

    Inventor： RUI RU CHEN SUU ,  MANDELMAN JACK ALLAN

    IPC: H01L27/04 ,  H01H85/00 ,  H01L21/60 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/525 ,  H01L23/528 ,  H01L27/06

    Abstract: PROBLEM TO BE SOLVED: To provide a fuse capable of electrically fusing off at ordinary operational power supply voltage, and also customizing duplication or other circuits at module level as well as fusing method. SOLUTION: Semiconductor fuse is provided between conductors 20 for connecting at least two wirings. This fuse contains spacers 30 arranged on adjacent conductors 20 and a fuse element 31 connected to the wirings 22 arranged between the spacers 30. The space between the conductors 20 contains the first width containing the minimum possible photolithographic width while the fuse element 31 is in the second width narrower than the first width.

    TRENCH CELL CAPACITOR
    6.
    发明专利
    TRENCH CELL CAPACITOR 失效

    公开(公告)号：JPH1074910A

    公开(公告)日：1998-03-17

    申请号：JP19424797

    申请日：1997-07-18

    Applicant: IBM ,  SIEMENS AG

    Inventor： ALSMEIER JOHANN ,  MANDELMAN JACK ALLAN ,  O'NEILL JAMES ANTHONY ,  PARKS CHRISTOPHER ,  PARRIES PAUL CHRISTIAN

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To obtain an integrated circuit capacitor of high capacitance by using an inversion layer inside a lightly doped substrate as a plate paired electrode for a capacitor. SOLUTION: A depletion region 302 is formed around a memory node 224 peripheral besides neighboring to an N-separation band 204 by forming an inversion node capacitor 200 on a P-substrate 202. An inversion region 304 is formed inside the depletion region 302 near the memory node 224. The inversion region is connected to the N-separation band 204. Accordingly, an electric field between the memory node 224 and the paired electrode of the inversion region 304 is partially defined by a work function difference between the N- separation band 204 and an N material inside the memory node 224. The N separation band 204 functions as a wiring connection to a common pared electrode of the inversion region 304 of the capacitor 200. Thereby, conductivity of the N separation band 204 plays a more important role than the designing of prior arts.

    FinFET WITH OVERLAP SENSITIVITY BETWEEN GATE AND FIN REDUCED
    7.
    发明专利
    FinFET WITH OVERLAP SENSITIVITY BETWEEN GATE AND FIN REDUCED 有权
    FinFET在栅极和熔化之间具有过大的灵敏度

    公开(公告)号：JP2008219002A

    公开(公告)日：2008-09-18

    申请号：JP2008035478

    申请日：2008-02-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MANDELMAN JACK ALLAN ,  LOUIS LU-CHEN HSU ,  CHENG KANGGUO ,  SHEETS JOHN EDWARD II

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66818

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a FinFET having a short fin having a uniform width. SOLUTION: There are provided a fin with a comparatively uniform width in a fin-type field effect transistor (FinFET) 100 and a device and a method for forming the same. A fin structure 110 can be formed so that the surface of a sidewall part of the fin structure is vertical with respect to a first crystal direction. A tapered region at the end portion of the fin structure can be vertical with respect to a second crystal direction. The fin structure can be subjected to a crystal-dependent etching. For a crystal-dependent etching, a material can be removed relatively quickly from the part of the fin vertical to the second crystal direction, and due to this, a fin structure with a comparatively uniform width can be brought about. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种形成具有均匀宽度的短鳍的FinFET的方法。 解决方案：在翅片型场效应晶体管（FinFET）100中提供了具有相对均匀宽度的鳍片，以及用于形成该鳍片的器件及其方法。 翅片结构110可以形成为使翅片结构的侧壁部分的表面相对于第一晶体方向垂直。 翅片结构的端部处的锥形区域可相对于第二晶体方向垂直。 翅片结构可以进行晶体依赖蚀刻。 对于晶体依赖的蚀刻，可以从翅片垂直于第二晶体方向的部分相对快速地去除材料，并且由此可以产生具有相对均匀的宽度的翅片结构。 版权所有（C）2008，JPO＆INPIT

    DEVICE HAVING ACTIVE SEMICONDUCTOR DEVICE AND FORMATION OF CONDUCTIVELY-CONNECTED ACTIVE DEVICE
    9.
    发明专利
    DEVICE HAVING ACTIVE SEMICONDUCTOR DEVICE AND FORMATION OF CONDUCTIVELY-CONNECTED ACTIVE DEVICE 失效

    公开(公告)号：JPH11317523A

    公开(公告)日：1999-11-16

    申请号：JP505799

    申请日：1999-01-12

    Applicant: IBM

    Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

    Abstract: PROBLEM TO BE SOLVED: To obtain a device, which has active devices formed on roughly continuous mesa regions, which are formed on more than one surfaces of an isolation region and consist of a semiconductor material, and conductive paths, which are formed on the mesa regions and are extended in the lengthwise directions of the mesa regions. SOLUTION: A semiconductor device has first active devices formed on mesa regions, which are formed by more than one sidewall of an isolation region 15 and consist of a semiconductor material, and conductive paths. The conductive paths are extended from the active devices to the lengthwise directions of the mesa regions. In one embodiment, a plurality of active devices are respectively formed on mesa region, and the active devices are connected electrically with each other through the mesa regions.

    10.
    发明专利
    未知

    公开(公告)号：DE602006008984D1

    公开(公告)日：2009-10-15

    申请号：DE602006008984

    申请日：2006-12-05

    Applicant: IBM

    Inventor： MANDELMAN JACK ALLAN ,  CHENG KANGGUO ,  HSU LOUIS LU-CHEN ,  YANG HAINING

    IPC: H01L29/786 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

    Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

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