公开(公告)号：EP1673809A4

公开(公告)日：2009-08-26

申请号：EP04795254

申请日：2004-10-14

Applicant: IBM

Inventor： MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D

IPC: H01L27/10 ,  H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and associated method for protecting an electrical structure (25) during a fuse link deletion by focused radiation (52). The structure (1 ) comprises a fuse element (2), a protection plate (10), a first dielectric layer (14), and a second dielectric layer (4). The structure (1) is formed within a semiconductor device (5). The protection plate (10) is formed within the first dielectric layer (14) using a damascene process. The second dielectric layer (4) is formed over the protection plate (10) and the first dielectric layer (14). The fuse element (2) is formed over the second dielectric layer (4). The fuse element (2) is adapted to be cut with a laser beam (52). The dielectric constant of the second dielectric layer (4) is greater than the dielectric constant of the first dielectric layer (14). The protection plate (10) is adapted to shield the first dielectric layer (14) from energy from the laser beam (52).

公开(公告)号：EP2020023A4

公开(公告)日：2012-09-19

申请号：EP07761307

申请日：2007-04-26

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

公开(公告)号：EP1687851A4

公开(公告)日：2011-02-23

申请号：EP04810291

申请日：2004-11-04

Applicant: IBM

Inventor： BADAMI DINESH A ,  LEE TOM C ,  LI BAOZHEN ,  MATUSIEWICZ GERALD ,  MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D ,  WATSON KIMBALL M ,  WYNNE JEAN E

IPC: H01L27/10 ,  H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC classification number: H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2007127816A2

公开(公告)日：2007-11-08

申请号：PCT/US2007067449

申请日：2007-04-26

Applicant: IBM ,  FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

Inventor： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads 37 with ball limiting metallization on an integrated circuit chip 30 by using a damascene process and preferably Cu metallization 32 in the chip 30 and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad 52 is formed in the top insulating layer 51 and it also serves as the final level of metallization in the chip.

Abstract translation: 一种用于在集成电路芯片30上通过使用镶嵌工艺，优选在芯片30中的铜金属化层32以及用于兼容性的球限制金属化中，优选地形成具有球限制金属化的Pb-铅C4连接或俘获垫37的方法。 在两个实施例中，捕获垫52形成在顶部绝缘层51中，并且还用作芯片中的最终金属化水平。

公开(公告)号：WO2005038876A3

公开(公告)日：2005-07-14

申请号：PCT/US2004034067

申请日：2004-10-14

Applicant: IBM ,  MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D

Inventor： MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D

IPC: H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and associated method for protecting an electrical structure (25) during a fuse link deletion by focused radiation (52). The structure (1 ) comprises a fuse element (2), a protection plate (10), a first dielectric layer (14), and a second dielectric layer (4). The structure (1) is formed within a semiconductor device (5). The protection plate (10) is formed within the first dielectric layer (14) using a damascene process. The second dielectric layer (4) is formed over the protection plate (10) and the first dielectric layer (14). The fuse element (2) is formed over the second dielectric layer (4). The fuse element (2) is adapted to be cut with a laser beam (52). The dielectric constant of the second dielectric layer (4) is greater than the dielectric constant of the first dielectric layer (14). The protection plate (10) is adapted to shield the first dielectric layer (14) from energy from the laser beam (52).

Abstract translation: 一种用于在通过聚焦辐射（52）的熔丝链断开期间保护电结构（25）的结构和相关方法。 结构（1）包括熔丝元件（2），保护板（10），第一介电层（14）和第二电介质层（4）。 结构（1）形成在半导体器件（5）内。 使用镶嵌工艺在第一介电层（14）内形成保护板（10）。 第二介质层（4）形成在保护板（10）和第一介电层（14）之上。 熔丝元件（2）形成在第二介质层（4）上。 熔丝元件（2）适于用激光束（52）切割。 第二介质层（4）的介电常数大于第一介电层（14）的介电常数。 保护板（10）适于屏蔽来自激光束（52）的能量的第一介电层（14）。

公开(公告)号：WO2005048304A3

公开(公告)日：2005-07-28

申请号：PCT/US2004036660

申请日：2004-11-04

Applicant: IBM ,  BADAMI DINESH A ,  LEE TOM C ,  LI BAOZHEN ,  MATUSIEWICZ GERALD ,  MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D ,  WATSON KIMBALL M ,  WYNNE JEAN E

Inventor： BADAMI DINESH A ,  LEE TOM C ,  LI BAOZHEN ,  MATUSIEWICZ GERALD ,  MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D ,  WATSON KIMBALL M ,  WYNNE JEAN E

IPC: H01L23/525 ,  H01L27/10 ,  H01L23/58 ,  H01L29/00

CPC classification number: H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract translation: 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。 熔丝连接在第一电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。

公开(公告)号：WO2008100923A3

公开(公告)日：2008-11-06

申请号：PCT/US2008053703

申请日：2008-02-12

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

IPC: B23K31/02 ,  H01L29/12

CPC classification number: H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/0501 ,  H01L2224/05083 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack (20') is deposited above a metal pad layer (19'). A top layer (22') of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer (21 ') of the barrier metal stack (20') removed by etching. The diffusion barrier (40) and C4 solder bump (50) may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

Abstract translation: 一种用于在形成用于BLM（限流冶金）的C4焊料凸块并提高C4间距时消除底切的系统和方法。 在该过程中，在金属垫层（19'）上方沉积阻挡层金属叠层（20'）。 通过CMP对阻挡层金属（例如Cu）的顶层（22'）进行图案化，通过蚀刻去除阻挡金属叠层（20'）的底部导电层（21'）。 扩散阻挡层（40）和C4焊料凸块（50）可以通过化学镀，在一个实施例中使用无掩模技术，或通过使用图案化掩模的电镀技术形成。 这样可以减少C4焊料凸点的间距。

公开(公告)号：WO2007146757A3

公开(公告)日：2008-03-20

申请号：PCT/US2007070661

申请日：2007-06-08

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In a first aspect, a method comprises depositing a first metal containing layer (16) into a trench structure, which contacts a metalized area (12) of a semiconductor structure (10). The method further includes patterning at least one opening in a resist to the first metal containing layer (16). The opening should be in alignment with the trench structure. At least a pad metal containing layer (20) is formed within the at least one opening (preferably by electroplating processes). The resist (18) and the first metal layer (16) underlying the resist (18) are then etched (with the second metal layer (20) acting as a mask, in embodiments). The method includes flowing solder material (22) within the trench and on pad metal containing layer (20) after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.

Abstract translation: 在第一方面，一种方法包括将第一含金属层（16）沉积到与半导体结构（10）的金属化区域（12）接触的沟槽结构中。 该方法还包括将抗蚀剂中的至少一个开口构图到第一含金属层（16）。 开口应与沟槽结构对齐。 在至少一个开口内（优选地，通过电镀工艺）形成至少一块垫金属层（20）。 然后在实施例中蚀刻抗蚀剂（18）和抗蚀剂（18）下面的第一金属层（16）（第二金属层（20）用作掩模）。 该方法包括在蚀刻工艺之后使沟槽内的焊料材料（22）和衬垫金属含有层（20）流动。 该结构是受控的崩溃芯片连接（C4）结构，包括至少一个以抗蚀剂图形形成的电镀金属层，以形成至少一个球限制冶金层。 该结构还包括没有底切的底层金属层。

公开(公告)号：DE112012004768T5

公开(公告)日：2014-11-06

申请号：DE112012004768

申请日：2012-08-29

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  QUESTAD DAVID L ,  SAUTER WOLFGANG ,  SULLIVAN TIMOTHY D

IPC: H01L23/48

Abstract: Ein topographisches Merkmal (305) ist in unmittelbarer Nähe zu einer leitfähigen Bond-Kontaktstelle (235) ausgebildet, die dazu verwendet wird, einen Lötkontakthügel (160) mit einem Halbleiter-Chip (140) zu verbinden. Das topographische Merkmal (305) ist durch einen Zwischenraum (310) von der leitfähigen Bond-Kontaktstelle (235) getrennt. Bei einer Ausführungsform ist das topographische Merkmal (305) an einer Stelle ausgebildet, die sich etwas jenseits der äußeren Begrenzung des Lötkontakthügels (160) befindet, wobei eine Kante des Kontakthügels (160) vertikal so ausgerichtet ist, dass sie mit dem Zwischenraum (310) zusammenfällt, der die leitfähige Bond-Kontaktstelle (235) von dem topographischen Merkmal (305) trennt. Das topographische Merkmal (305) stellt eine Erhöhung der Dicke einer nichtleitfähigen Schicht (240), die über dem Halbleiter-Chip (140) und der leitfähigen Bond-Kontaktstelle (235) angeordnet ist, und eine Verspannungspufferung bereit.