公开(公告)号：JPS6369238A

公开(公告)日：1988-03-29

申请号：JP19654787

申请日：1987-08-07

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  JOHNSON DAVID LOUIS ,  PAN PAI-HUNG ,  PAQUETTE CHARLES ARTHUR

IPC: H01L21/316 ,  H01L21/265 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51

公开(公告)号：JPH1050943A

公开(公告)日：1998-02-20

申请号：JP12686997

申请日：1997-05-16

Applicant: IBM

Inventor： GOLDEN KEVIN M ,  PAN PAI-HUNG ,  STEWART KEVIN J ,  THOMAS ALAN C

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To get a trench capacitor, which has buried plates in high integration density, by a simple method, by including a stage of etching a diffusion source, according to the nonexposed section of resist, and a stage of completing a trench capacitor. SOLUTION: A trench 210 is etched within a substrate 110, according to a TEOS layer 140 made by pattern. Then in order to fill up the trench 210 surely, resist is made poor in temperature stability so that the reflow of the resist may be executed at high temperature after adhesion. Next, the resist is provided with a recess as far as about 1.5 micron below the substrate by exposure and development. Then, the trench is filled up with n+ polycrystalline silicon or other proper material. Next, using reactive ion etching, the filler is lowered to about 1.2μm from the surface of the substrate. The residual part of the trench is fill up again with n+ polycrystalline silicon or other proper material, and it is slightly lowered by RIE or other proper etching method, whereupon it is completed.

公开(公告)号：CA1306072C

公开(公告)日：1992-08-04

申请号：CA556673

申请日：1988-01-15

Applicant: IBM

Inventor： CRONIN JOHN E ,  KAANTA CARTER W ,  LEACH MICHAEL A ,  LEE PEI-ING P ,  PAN PAI-HUNG

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L21/285 ,  H01L29/40 ,  H01L23/48

Abstract: B??-86-011 The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin layer of titanium nitride and a thick layer of a refractory metal, e.g., tungsten or molybdenum, overlying the titanium nitride layer.

公开(公告)号：DE3774052D1

公开(公告)日：1991-11-28

申请号：DE3774052

申请日：1987-08-21

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  JOHNSON DAVID LOUIS ,  PAN PAI-HUNG ,  PAQUETTE CHARLES ARTHUR

IPC: H01L21/316 ,  H01L21/265 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51

Abstract: The inventive method relates to the formation of a thin film of silicon oxynitride exhibiting a high breakdown voltage on a silicon substrate of a first conductivity type and comprises the steps of: forming a thin film of silicon oxynitride on the silicon substrate; forming a region of a second conductivity type in at least part of the silicon substrate by ion implantation through said thin film of silicon oxynitride; and annealing said silicon oxynitride film in a wet O2 ambient at a temperature between 700 DEG C and 1000 DEG C. Preferably the deposited layer is annealed additionally after the deposition and prior to the ion implantation. The method is applied in the formation of capacitor structures, like high capacitance storage capacitors for dynamic random access memory cells.

公开(公告)号：DE3685224D1

公开(公告)日：1992-06-17

申请号：DE3685224

申请日：1986-01-17

Applicant: IBM

Inventor： GEIPEL JR ,  PAN PAI-HUNG

IPC: H01L21/76 ,  H01L21/314 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

Abstract: An oxygen-impervious pad structure (100) which reduces the bird's beak profiles in semi-recessed oxide isolation regions. The sidewalls of a conventional silicon oxide (12) - silicon nitride (14) pad are coated with a thick layer (20) of oxynitride. A thin layer (18) of oxynitride is grown on the substrate surface prior to deposition of the thick oxynitride layer. The thick oxynitride layer prevents lateral oxidizing specie diffusion through the oxide layer of the conventional pad, and the thin oxynitride layer prevents oxidizing specie diffusion through the pad-substrate interface into the substrate region beneath the pad.

公开(公告)号：CA2051566A1

公开(公告)日：1992-04-25

申请号：CA2051566

申请日：1991-09-17

Applicant: IBM

Inventor： DOBUZINSKY DAIVD M ,  HARMON DAVID L ,  KASI SRINANDAN R ,  KENNEY DONALD M ,  NGUYEN SON V ,  NGUYEN TUE ,  PAN PAI-HUNG

IPC: C23C8/36 ,  H01L21/31 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  C23C4/02 ,  C23C4/04 ,  H01L21/76

Abstract: U9-90-033 A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree.C, preferably about 350-400.degree.C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (