公开(公告)号：JP2003218177A

公开(公告)日：2003-07-31

申请号：JP2003008636

申请日：2003-01-16

Applicant: IBM

Inventor： MAGERLEIN JOHN HAROLD ,  MCKNIGHT SAMUEL ROY ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VAN HORN JOSEPH J ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: G01R31/26 ,  G01R1/04 ,  H01L21/60 ,  H01L21/66 ,  H05K3/24 ,  H05K3/32

Abstract: PROBLEM TO BE SOLVED: To provide an ability to test and 'burn in' device chips that require ultra high pitch I/O pads. SOLUTION: A system for testing a collection of the device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; the carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2007305986A

公开(公告)日：2007-11-22

申请号：JP2007120486

申请日：2007-05-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KATHERINE L SAENGER ,  CHRISTOPHER V JAHNES ,  SATYANARAYANA V NITTA ,  PETRARCA KEVIN SHAWN

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a multilevel interconnect structure including air gaps and a method of fabricating the structure. SOLUTION: The multilevel interconnect structure including air gaps includes an assembly of interspersed line levels and via levels, in which the via level includes one or more conductive vias embedded in a dielectric layer and the dielectric layer in the via level is a solid arranged under and above the line structures of adjacent levels with perforations formed between the line structures. The line level includes conductive lines and dielectrics inclusive of air gaps. A solid dielectric bridge layer, which includes conductive contacts and is formed by filling in a perforated dielectric layer, is disposed above the assembly of the line levels and via levels interspersed with each other. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供包括气隙的多层互连结构和制造该结构的方法。

解决方案：包括气隙的多层互连结构包括散布的线路电平和通路电平的组件，其中通路电平包括嵌入电介质层中的一个或多个导电通孔，并且通孔级中的电介质层是固体 布置在相邻层次的线结构下方和上方，其中线结构之间形成有穿孔。 线路电平包括导线和包括气隙的电介质。 包括导电触点并且通过填充有孔电介质层形成的固体介质桥接层设置在彼此散布的线路电平和通路电平的组合之上。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003273158A

公开(公告)日：2003-09-26

申请号：JP2003003619

申请日：2003-01-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FURMAN BRUCE KENNETH ,  SURENDRA MAHESWARAN ,  GOMA SHERIF A ,  KARECKI ANNA ,  KARECKI SIMON M ,  MAGERLEIN JOHN HAROLD ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: H01L23/52 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/60 ,  H05K1/03 ,  H05K1/11 ,  H05K3/38

CPC classification number: H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13582 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: PROBLEM TO BE SOLVED: To provide a system making an interconnection with a quite high density by connecting device chips and a chip carrier by using a microjoint interconnect structure.
SOLUTION: In the system, a pair of device chips is mounted on a microjoint interconnect chip carrier by using a microjoint interconnect structure. The microjoint interconnect chip carrier comprises a multilayer substrate having a plurality of receptacles on its surface. A pair of microjoint interconnect pads corresponding to the receptacles is provided on the device chips. Interconnecting wiring enabling an interconnection between the device chips is provided between the receptacles.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：通过使用微型连接互连结构，通过连接器件芯片和芯片载体来提供使密度相当高的互连的系统。 解决方案：在系统中，通过使用微型连接互连结构将一对器件芯片安装在微型连接互连芯片载体上。 微型连接互连芯片载体包括其表面上具有多个插座的多层基板。 在器件芯片上设置一对对应于插座的微接点互连焊盘。 在插座之间设置能够实现器件芯片之间的互连的互连布线。 版权所有（C）2003，JPO

公开(公告)号：AU2002363902A8

公开(公告)日：2003-07-30

申请号：AU2002363902

申请日：2002-12-19

Applicant: IBM

Inventor： PETRARCA KEVIN SHAWN ,  SAMBUCETTI CARLOS JUAN ,  PURUSHOTHAMAN SAMPATH ,  VOLANT RICHARD PAUL ,  MAGERLEIN JOHN HAROLD ,  WALKER GEORGE FREDERICK

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

公开(公告)号：AU2002363902A1

公开(公告)日：2003-07-30

申请号：AU2002363902

申请日：2002-12-19

Applicant: IBM

Inventor： MAGERLEIN JOHN HAROLD ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

公开(公告)号：CA2472750A1

公开(公告)日：2003-07-24

申请号：CA2472750

申请日：2002-12-19

Applicant: IBM

Inventor： WALKER GEORGE FREDERICK ,  VOLANT RICHARD PAUL ,  MAGERLEIN JOHN HAROLD ,  SAMBUCETTI CARLOS JUAN ,  PURUSHOTHAMAN SAMPATH ,  PETRARCA KEVIN SHAWN

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

公开(公告)号：AU2021399002B2

公开(公告)日：2025-02-06

申请号：AU2021399002

申请日：2021-12-13

Applicant: IBM

Inventor： ABRAHAM DAVID ,  DIAL OLIVER ,  COTTE JOHN ,  PETRARCA KEVIN SHAWN

IPC: H01L21/768 ,  G06N10/40 ,  H01L23/00 ,  H01L25/065

Abstract: A device (500) comprises a first chip (508) having a first chip front-side and a first chip back-side, a qubit chip (504) having a qubit chip front-side and a qubit chip back-side, the qubit chip front-side operatively coupled to the first chip front-side with a set of bump-bonds (506), a set of through-silicon vias (TSVs) connected to at least one of the first chip back-side or the qubit chip back-side, and a cap wafer (502) that is metal bonded to at least one of the qubit chip back-side or the first chip back-side. Preferably, the qubits and the TSVs are superconducting, and the cap wafer features a cavity that comprises a metal coating on its inside surface for electromagnetic shielding.

公开(公告)号：CA2472750C

公开(公告)日：2009-02-03

申请号：CA2472750

申请日：2002-12-19

Applicant: IBM

Inventor： VOLANT RICHARD PAUL ,  SAMBUCETTI CARLOS JUAN ,  PURUSHOTHAMAN SAMPATH ,  PETRARCA KEVIN SHAWN ,  WALKER GEORGE FREDERICK ,  MAGERLEIN JOHN HAROLD

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer , barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer an d a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.