公开(公告)号：EP2036130A4

公开(公告)日：2009-12-23

申请号：EP07797521

申请日：2007-05-17

Applicant: IBM

Inventor： LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

IPC: H01L29/76

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

公开(公告)号：JP2003060085A

公开(公告)日：2003-02-28

申请号：JP2002184151

申请日：2002-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ROVEDO NIVO ,  LAM CHUNG H ,  MIH REBECCA D

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/10867

Abstract: PROBLEM TO BE SOLVED: To provide an integrated process at a low cost, with forms a logic circuit including an embedded DRAM array while still preserving the advantages of the logic circuit and a DRAM circuit to the maximum extent possible.
SOLUTION: The logic circuit including an embedded DRAM achieves process integration by simultaneously forming a strap connecting a memory cell capacitor with a pass transistor, and a buried dielectric layer isolating logic transistor sources and drains from a substrate.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了提供低成本的集成处理，形成包括嵌入式DRAM阵列的逻辑电路，同时尽可能地保持逻辑电路和DRAM电路的优点。 解决方案：包括嵌入式DRAM的逻辑电路通过同时形成将存储单元电容器与传输晶体管连接的带以及掩埋介电层隔离逻辑晶体管源和衬底的漏极来实现工艺集成。

公开(公告)号：JPS62105426A

公开(公告)日：1987-05-15

申请号：JP23024186

申请日：1986-09-30

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SCHULZ RONALD N

IPC: G03F1/00 ,  G03F1/08 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311

公开(公告)号：WO2007140130A3

公开(公告)日：2009-04-09

申请号：PCT/US2007069100

申请日：2007-05-17

Applicant: IBM ,  LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

Inventor： LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

IPC: H01L29/76

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract translation: 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

公开(公告)号：WO0247144A3

公开(公告)日：2003-02-13

申请号：PCT/US0145195

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHEN BOMY A ,  HIRSCH ALEXANDER ,  IYER SUNDAR K ,  ROVEDO NIVO ,  WANN HSING-JEN ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/7621 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/823481

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract translation: 在源极和漏极之下形成图案化的掩埋绝缘体，通过在身体区域上形成掩模并在要形成源极和漏极的区域中注入一定量的n或p型离子，然后蚀刻STI并蚀刻出植入 区。 光氧化之后是STI中的共形氧化物沉积以及蚀刻区域，从而仅在需要时形成掩埋氧化物。

公开(公告)号：JP2007134718A

公开(公告)日：2007-05-31

申请号：JP2006303401

申请日：2006-11-08

Applicant: Chartered Semiconductor Mfg Ltd ,  Internatl Business Mach Corp ,  Samsung Electronics Co Ltd ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  サムスン エレクトロニクス カンパニー リミテッド ,  チャータード・セミコンダクター・マニュファクチャリング・リミテッド

Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

IPC: H01L21/8238 ,  C23C16/34 ,  H01L21/318 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/823807

Abstract: PROBLEM TO BE SOLVED: To provide a SMT (stress memory technique) for both of an nFET and a pFET.
SOLUTION: The method includes forming a tensile stress layer 120 over the nFET 104 and a compressive stress layer 122 over the pFET 106, annealing 150 to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer 122 may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include the one used in a temperature of approximately 400-1,200°C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET 106.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为nFET和pFET两者提供SMT（应力记忆技术）。 解决方案：该方法包括在nFET104上形成拉伸应力层120，在pFET 106上形成压应力层122，退火150以将应力记忆在半导体器件中并除去应力层。 压应力层122可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括在约400-1200℃的温度下使用的退火步骤。 高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET 106中。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：JPS62101034A

公开(公告)日：1987-05-11

申请号：JP19302286

申请日：1986-08-20

Applicant: IBM

Inventor： BEYER KLAUS DIETRICH ,  MAKRIS JAMES STEVE ,  MENDEL ERIC ,  NUMMY KAREN ANN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

公开(公告)号：AT521089T

公开(公告)日：2011-09-15

申请号：AT07797521

申请日：2007-05-17

Applicant: IBM

Inventor： LI JINGHONG ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

IPC: H01L29/76

Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

公开(公告)号：CA1290079C

公开(公告)日：1991-10-01

申请号：CA601597

申请日：1989-06-02

Applicant: IBM

Inventor： AKBAR SHAH ,  KROESEN PATRICIA L ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/72 ,  H01L29/52 ,  H01L29/60

Abstract: VERTICAL BIPOLAR TRANSISTOR A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer;a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect disposed on a surface of the base contact extension layer and; a collector contact extension layer formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers. FI9-87-027

公开(公告)号：CA2011233A1

公开(公告)日：1990-12-09

申请号：CA2011233

申请日：1990-03-01

Applicant: IBM

Inventor： CODELLA CHRISTOPHER F ,  ROVEDO NIVO ,  OGURA SEIKI

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

Abstract: FIELD-EFFECT-TRANSISTOR WITH ASYMMETRICAL STRUCTURE A field effect transistor of asymmetrical structure comprises: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; and a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region. The transistor can further beneficially comprise a halo region of the first conductivity type in the substrate generally surrounding only the source region.