公开(公告)号：JPH1012819A

公开(公告)日：1998-01-16

申请号：JP7316397

申请日：1997-03-26

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent high leak current and shot-circuiting, by forming a capaci tor between interconnection wiring layers of a semiconductor chip having a clean interface free from residue produced by treatment. SOLUTION: A capacitor 20 is formed between a mutual connection wiring 12 of a first level and an interconnection wiring layer 11 of a second level. A via 36 electrically connects the capacitor 20 with the mutual connection wiring 11 of the second level. The interconnection wiring 12 of the first level is used as a lower electrode of the capacitor 20, i.e., a base electrode, and connected with a lower via 30. The via 30 is formed in dielectric 22 and mutually connected with a lower conducting region. The dielectrics layer 22 and the upper surface of the via 30 are polished, and an insulating region and the conducting region form the same surface 31. The capacitor 20 is constituted of e.g. the interconnection wiring 12 of the first level, a dielectrics layer 14 and a layer of an upper electrode or a facing electrode 16. The upper electrode 16 is so formed that its peripheral edge is positioned inside the peripheral edge of the dielectrics layer 14.

公开(公告)号：JP2004025431A

公开(公告)日：2004-01-29

申请号：JP2003065512

申请日：2003-03-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VOLANT RICHARD P ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  DAVID M ROCKWELL ,  STEIN KENNETH JAY

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  B81C99/00 ,  H01H59/00

CPC classification number: H01H59/0009 ,  B81B3/0021 ,  B81B2201/018 ,  B81B2203/058 ,  B81B2207/015 ,  B81C1/00214 ,  H01H2001/0068 ,  H01H2059/0054

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor torsional micro-electromechanical (MEM) switch which has a control electrode being almost perpendicular to a switching electrode, applies an electrical separation between the control signal and a switch signal, is equipped with a plurality of control parts for opening/closing switches, and whole switching area arranged in various multiple-pole, multiple-throw is remarkably reduced.
SOLUTION: The switch is equipped with a conductive movable control electrode 50 and an insulated semiconductor torsion beam 60 attached to the movable control electrode, the insulated torsion beam and the movable control electrode being parallel to each other, and a movable contact 20 attached to the insulated torsion beam, wherein the combination of the insulated torsion beam and the control electrode is perpendicular to the movable contact. The torsional MEM switch has the control electrodes almost perpendicular to the switching electrodes. The MEM switch has a plurality of control parts to activate the device to form a single-pole, single-throw switch or a multiple-pole, multiple-throw switch. The manufacturing method of the torsional MEM switch is completely compatible with the CMOS manufacturing process.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2005217419A

公开(公告)日：2005-08-11

申请号：JP2005021309

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  ANDRICACOS PANAYOTIS C ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  MAGERLEIN JOHN H ,  PETRARCA KEVIN S ,  STEIN KENNETH JAY ,  VOLANT RICHARD P

IPC: H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08

CPC classification number: H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an inductor and a method of forming the inductor. SOLUTION: The method of forming the inductor comprises (a) a step for providing a semiconductor substrate, (b) a step for forming a dielectric layer on the surface of the substrate, (c) a step for forming a lower trench in the dielectric layer, (d) a step for forming a resist layer on the surface of the dielectric layer, (e) a step for forming an upper trench which is aligned to the lower trench and whose bottom is opened for the lower trench in the resist layer, and (f) a step for completely filling the lower trench with a conductor and at least partially filling the upper trench with the conductor to form the inductor. The semiconductor structure includes the inductor including the upper surface, bottom surface and sidewall and a means that allows the inductor to be electrically contacted, the lower section of the inductor is extended by a distance that the lower section of the inductor is fixed in the dielectric layer formed on the substrate, and the upper section thereof is extended on the dielectric layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供电感器和形成电感器的方法。 形成电感器的方法包括（a）提供半导体衬底的步骤，（b）在衬底的表面上形成电介质层的步骤，（c）形成下沟槽的步骤 在电介质层中，（d）在电介质层的表面上形成抗蚀剂层的步骤，（e）形成上沟槽的步骤，该上沟槽与下沟槽对准并且底部为下沟槽开口 抗蚀剂层，和（f）用导体完全填充下沟槽并且至少部分地用导体填充上沟槽以形成电感器的步骤。 半导体结构包括电感器，其包括上表面，底表面和侧壁，以及允许电感器电接触的装置，电感器的下部延伸一段距离，电感器的下部固定在电介质中 层，其上部在电介质层上延伸。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004006310A

公开(公告)日：2004-01-08

申请号：JP2003109122

申请日：2003-04-14

Applicant: IBM

Inventor： VOLANT RICHARD P ,  ANGELL DAVID ,  CANAPERI DONALD F ,  KOCIS JOSEPH T ,  PETRARCA KEVIN S ,  STEIN KENNETH JAY ,  WILLE WILLIAM C

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method of a microelectric mechanical switch (MEMS) device provided with a self-alignment spacer or a bump. SOLUTION: The spacers arranged having the optimum size so as to make to the minimum a problem caused by stiction by functioning as restricting mechanism concerning the switch are designed. The spacers are manufactured by using the typically standard semi-conductor technology used for manufacturing a CMOS device. This method to manufacture these spacers does not need an additional deposition, excessive lithography process, and an additional etching. COPYRIGHT: (C)2004,JPO

公开(公告)号：DE69712968T2

公开(公告)日：2003-01-16

申请号：DE69712968

申请日：1997-03-17

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/3205 ,  H01L23/64

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring (12,11) separated by a first dielectric (35), a capacitor (20) formed by a second dielectric (14), a bottom electrode of the lower interconnection wiring (12) or a via and a top electrode of the upper interconnection wiring or a separate metal layer (17,18,19). The system overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

公开(公告)号：DE69016326D1

公开(公告)日：1995-03-09

申请号：DE69016326

申请日：1990-05-12

Applicant: IBM

Inventor： NGUYEN THAO NGOC ,  STEIN KENNETH JAY ,  SUN YUAN-CHEN ,  WEINBERG ZEEV AVRAHAM

IPC: C23C16/30 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  C23C16/34 ,  C23C16/40

Abstract: A system for fabricating an ultra-thin composite dielectric, usable for the capacitor in DRAM and in other integrated circuits, involving the deposition, a LPCVD tube, of a nitride (3) in situ on a very thin LPCVD oxide (2). By re-oxidizing the nitride (3) or depositing a LPCVD oxide layer (4, 4 min ) in situ thereon, a composite ONO dielectric, having very low defect density and good overall electric properties, of less than 10 nm in thickness and as low as 4.5 nm, may be formed.

公开(公告)号：DE69712968D1

公开(公告)日：2002-07-11

申请号：DE69712968

申请日：1997-03-17

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/3205 ,  H01L23/64

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring (12,11) separated by a first dielectric (35), a capacitor (20) formed by a second dielectric (14), a bottom electrode of the lower interconnection wiring (12) or a via and a top electrode of the upper interconnection wiring or a separate metal layer (17,18,19). The system overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

公开(公告)号：DE69016326T2

公开(公告)日：1995-07-13

申请号：DE69016326

申请日：1990-05-12

Applicant: IBM

Inventor： NGUYEN THAO NGOC ,  STEIN KENNETH JAY ,  SUN YUAN-CHEN ,  WEINBERG ZEEV AVRAHAM

IPC: C23C16/30 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  C23C16/34 ,  C23C16/40

Abstract: A system for fabricating an ultra-thin composite dielectric, usable for the capacitor in DRAM and in other integrated circuits, involving the deposition, a LPCVD tube, of a nitride (3) in situ on a very thin LPCVD oxide (2). By re-oxidizing the nitride (3) or depositing a LPCVD oxide layer (4, 4 min ) in situ thereon, a composite ONO dielectric, having very low defect density and good overall electric properties, of less than 10 nm in thickness and as low as 4.5 nm, may be formed.