公开(公告)号：EP1841558A4

公开(公告)日：2012-04-04

申请号：EP05852628

申请日：2005-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER ENAMUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00 ,  B23H5/08

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

公开(公告)号：EP1883961A4

公开(公告)日：2012-12-05

申请号：EP06759690

申请日：2006-05-12

Applicant: IBM

Inventor： CASEY JON A ,  BERGER MICHAEL ,  BUCHWALTER LEENA P ,  CANAPERI DONALD F ,  HORTON RAYMOND R ,  JAIN ANURAG ,  PERFECTO ERIC D ,  TORNELLO JAMES A

IPC: H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2006088533A3

公开(公告)日：2007-09-27

申请号：PCT/US2005043464

申请日：2005-12-02

Applicant: IBM ,  ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract translation: 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：WO2006124607A3

公开(公告)日：2007-04-12

申请号：PCT/US2006018458

申请日：2006-05-12

Applicant: IBM ,  CASEY JON A ,  BERGER MICHAEL ,  BUCHWALTER LEENA P ,  CANAPERI DONALD F ,  HORTON RAYMOND R ,  JAIN ANURAG ,  PERFECTO ERIC D ,  TORNELLO JAMES A

Inventor： CASEY JON A ,  BERGER MICHAEL ,  BUCHWALTER LEENA P ,  CANAPERI DONALD F ,  HORTON RAYMOND R ,  JAIN ANURAG ,  PERFECTO ERIC D ,  TORNELLO JAMES A

IPC: H01L23/22 ,  H01L23/04 ,  H01L23/14 ,  H01L23/24

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via (100) at an elevated temperature, A supply chamber (630) is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Abstract translation: 使用无粘性，低粘度，高温稳定的聚合物或低粘度的高固含量聚合物溶液密封通孔，其中聚合物材料在高温下浸渍在通孔（100）内，引入供应室（630） 以在升高的温度下施用聚合物材料，通常在高至足以液化聚合物材料的温度下。 聚合物材料通过来自泵，活塞或保持在所述供应室内的真空的力的加热供应管线引入。

公开(公告)号：JP2004146800A

公开(公告)日：2004-05-20

申请号：JP2003313299

申请日：2003-09-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CANAPERI DONALD F ,  DALTON TIMOTHY J ,  GATES STEPHEN M ,  KRISHNAN MAHADEVAIYER ,  PURUSHOTHAMAN SAMPATH ,  SMITH SEAN P E ,  NITTA SATYA

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which realizes high performance interconnection including copper wiring and an insulator having an extremely low dielectric constant (k). SOLUTION: In this structure, wiring is supported by a low-k dielectric material having relatively high durability, such as SiLk(R) or SiO 2 , and then the remaining spaces in the structure are filled with a gap filling dielectric material that has an extremely low-k and a small hardness. Accordingly, in the structure, durable layers for obtaining the strength are bonded with an extremely low-k dielectric material for achieving electric performance of the interconnection. As a result, damages to and an increase in dielectric constant of the extremely low-k dielectric material caused during the manufacturing process are avoided, and delamination in the structure during the metal chemical mechanical polishing processes is prevented. Further, photoresist poisoning troubles caused by interaction with the extremely low-k dielectric material can be removed. COPYRIGHT: (C)2004,JPO

公开(公告)号：JPH11330025A

公开(公告)日：1999-11-30

申请号：JP5812699

申请日：1999-03-05

Applicant: IBM

Inventor： CANAPERI DONALD F ,  JAGANNATHAN RANGARAJAN ,  MAHAADEVIIERU KURISHUNAN ,  CLIFFORD OWEN MORGAN ,  WRIGHT TERRANCE M

IPC: B24B37/00 ,  C09K13/00 ,  H01L21/304 ,  H01L21/3105

Abstract: PROBLEM TO BE SOLVED: To enable a first film to align when a second film on a plane by adding triethanolamine to a polishing slurry, which reacts with the first film and with the second film of a second material under a predetermined part of the first film, to increase the reactivity with respect to the first film and by exposing the second film by interrupting the polishing, when the first film is removed completely. SOLUTION: In order to control the polishing speed of the material of a composite material substrate, the substrate having a first film formed of a first material and a second film formed of a second material lying under a predetermined part of the first film is chemical-mechanical polished using a slurry reacting, with the first and second films so as to remove the most part of the first film. Then, adequate amount of triethanolamine is added to the slurry for increasing the reactivity of the slurry with the first film and chemical- mechanical polishing is carried out. Thereupon, the residual part of the first film is removed, and if the polishing is interrupted when the first film on the part under which second film lies is removed completely, a specified part is exposed so that the first film is aligned with the second film on a plane.

公开(公告)号：JP2004006310A

公开(公告)日：2004-01-08

申请号：JP2003109122

申请日：2003-04-14

Applicant: IBM

Inventor： VOLANT RICHARD P ,  ANGELL DAVID ,  CANAPERI DONALD F ,  KOCIS JOSEPH T ,  PETRARCA KEVIN S ,  STEIN KENNETH JAY ,  WILLE WILLIAM C

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method of a microelectric mechanical switch (MEMS) device provided with a self-alignment spacer or a bump. SOLUTION: The spacers arranged having the optimum size so as to make to the minimum a problem caused by stiction by functioning as restricting mechanism concerning the switch are designed. The spacers are manufactured by using the typically standard semi-conductor technology used for manufacturing a CMOS device. This method to manufacture these spacers does not need an additional deposition, excessive lithography process, and an additional etching. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003109918A

公开(公告)日：2003-04-11

申请号：JP2001300046

申请日：2001-09-28

Applicant: IBM

Inventor： CANAPERI DONALD F ,  COHEN GUY ,  RYAN HAN ,  OTT JOHN A ,  LOFARO MICHAEL ,  CHU JACK O

IPC: B24B37/00 ,  C08J5/14 ,  C09K3/14 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method and device by which a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool can be incorporated. SOLUTION: CMP is performed with a descending force of 1 psi, backward air pressure of 0.5 psi, platen speed of 50 rpm, carrier speed of 30 rpm, and slurry flow rate of 140 milliliter.

公开(公告)号：MY126089A

公开(公告)日：2006-09-29

申请号：MYPI20014195

申请日：2001-09-06

Applicant: IBM

Inventor： CANAPERI DONALD F ,  CHU JACK OON ,  EMIC CHRISTOPHER P D ,  HUANG LIJUAN ,  OTT JOHN ALBERT ,  WONG HON-SUM PHILIP

IPC: H01L21/36 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/778 ,  H01L29/786 ,  H01L29/812

Abstract: A METHOD FOR FORMING STRAINED SI OR SIGE ON RELAXED SIGE ON INSULATOR (SGOJ) IS DESCRIBED INCORPORATING GROWING EPITAXIAL SI1GE LAYERS ON A SEMICONDUCTOR SUBSTRATE, IMPLANTING HYDROGEN INTO A SELECTED SI1..GE LAYER TO FORM A HYDROGENERICH DEFECTIVE LAYER, SMOOTHING SURFACES BY CHEMO-MECHANICAL POLISHING, BONDING TWO SUBSTRATES TOGETHER VIA THEXMAL TREATMENTS AND SEPARATING TWO SUBSTRATES AT THE HYDROGEN-RICH DEFECTIVE LAYER. THE SEPARATED SUBSTRATES MAY HAVE ITS UPPER SURFACE SMOOTHED BY CMI’ FOR EPITAXIAL DEPOSITION OF RELAXED SI,GE,,, AND STRAINED SI1GE DEPENDING UPON COMPOSITION, STRAINED SI, STRAINED SIC, STRAINED GE, STRAINED GEC, AND STRAINED SI3GEC.