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公开(公告)号：GB2581693B
公开(公告)日：2022-01-12
申请号：GB202006469
申请日：2018-08-02
Applicant: IBM
Inventor： GIORA BIRAN , PREETHAM LOBO , TOBIAS WEBEL , ALPER BUYUKTOSUNOGLU , CHRISTOS VEZYRTZIS , RAMON BERTRAN MONFORT , PIERCE I-JEN CHUANG , PHILLIP JOHN RESTLE , PRADIP BOSE
Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
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公开(公告)号：GB2632957A
公开(公告)日：2025-02-26
申请号：GB202416053
申请日：2023-01-17
Applicant: IBM
Inventor： ADAM COLLURA , MICHAEL ROMAIN , WILLIAM HUOTT , PAWEL OWCZARCZYK , CHRISTIAN JACOBI , ANTHONY SAPORITO , CHUNG-LUNG SHUM , ALPER BUYUKTOSUNOGLU , TOBIAS WEBEL , MICHAEL CADIGAN JR , PAUL LOGSDON , SEAN CAREY , KARL ANDERSON , MARK CICHANOWSKI , STEFAN PAYER
Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. The method includes detecting a region, such as an individual processor, of a processor chip exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life. The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltage spikes back to within some pre-specified range. The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.
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公开(公告)号：GB2532210A
公开(公告)日：2016-05-18
申请号：GB201420013
申请日：2014-11-11
Applicant: IBM
Inventor： TOBIAS WEBEL , MALCOLM S WARE , MICHAEL S FLOYD , CHARLES LEFURGY , KARTHICK RAJAMANI , ALAN DRAKE
IPC: G06F1/32
Abstract: Disclosed is a method of managing a multicore processor with a common supply rail connecting the processor cores. The method detects the core units indicating an idle state exits, and delays a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number. This is to reduce voltage droops due to several processor cores leaving the idle state at the same time and thus reduce the noise generated in the processor. The detecting may take place in a window of a set number of clock cycles, and the delaying may comprise throttling or postponing the command execution. The processor may have core power management logic with idle state exit register for turning on or off outputting an idle state value.
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公开(公告)号：GB2581693A
公开(公告)日：2020-08-26
申请号：GB202006469
申请日：2018-08-02
Applicant: IBM
Inventor： GIORA BIRAN , PREETHAM LOBO , TOBIAS WEBEL , ALPER BUYUKTOSUNOGLU , CHRISTOS VEZYRTZIS , RAMON BERTRAN MONFORT , PIERCE I-JEN CHUANG , PHILLIP JOHN RESTLE , PRADIP BOSE
Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
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