公开(公告)号：US20250006822A1

公开(公告)日：2025-01-02

申请号：US18708028

申请日：2023-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Na Zhou ,  Junjie Li ,  Jianfeng Gao ,  Tao Yang ,  Junfeng Li ,  Jun Luo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.

公开(公告)号：US20250157816A1

公开(公告)日：2025-05-15

申请号：US18933956

申请日：2024-10-31

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinbiao Liu ,  Jun Luo ,  Junfeng Li ,  Xiaobin He ,  Tao Yang

IPC: H01L21/02 ,  H01L21/306

Abstract: The present disclosure relates to a method of obtaining a nanoscale line by using a laser, including: forming a dielectric layer and an amorphous silicon layer on a substrate sequentially; irradiating a mask plate by using the laser to perform a silicon crystallization in a partial region of the amorphous silicon layer, where a grain boundary of a polycrystalline silicon formed by the silicon crystallization in the partial region of the amorphous silicon layer is determined by a spacing between holes with a regular shape on the mask plate; performing a planarization process on the grain boundary of the polycrystalline silicon of the amorphous silicon layer; removing the grain boundary by using a corrosion solution to form a grain boundary trench; and obtaining the nanoscale line on the substrate by using the grain boundary trench.

公开(公告)号：US10157956B2

公开(公告)日：2018-12-18

申请号：US15477191

申请日：2017-04-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hushan Cui ,  Jinjuan Xiang ,  Xiaobin He ,  Tao Yang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/00 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/0232

Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m≥1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

公开(公告)号：US20150287606A1

公开(公告)日：2015-10-08

申请号：US14744835

申请日：2015-06-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qiang Xu ,  Chao Zhao ,  Jun Luo ,  Guilei Wang ,  Tao Yang ,  Junfeng Li

IPC: H01L21/285 ,  H01L21/28

CPC classification number: H01L21/28562 ,  C23C16/0272 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/76876 ,  H01L21/76877 ,  H01L29/66545

Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.

Abstract translation: 公开了沉积钨（W）层的方法。 一方面，该方法包括在衬底的表面上沉积SiH 4基底W膜以预处理该表面。 该方法包括在预处理的表面上沉积B2H6基底W层。 SiH4基底W膜可以是几个原子层厚。 膜和基底W层可以沉积在单个ALD工艺中，包括反应气体浸泡，反应气体引入和主沉积操作。 形成膜可以包括在气体浸泡操作期间将SiH 4气体引入反应腔中，并且在气体引入操作期间将SiH 4和WF 6气体引入空腔。 SiH4和WF6气体可以根据待沉积的钨层的厚度交替地引入多个循环。

公开(公告)号：US20250063713A1

公开(公告)日：2025-02-20

申请号：US18799167

申请日：2024-08-09

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng GAO ,  Weibing LIU ,  Junjie LI ,  Na ZHOU ,  Tao Yang ,  Junfeng LI ,  Jun LUO

IPC: H10B12/00

Abstract: The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.

公开(公告)号：US09589809B2

公开(公告)日：2017-03-07

申请号：US14744835

申请日：2015-06-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qiang Xu ,  Chao Zhao ,  Jun Luo ,  Guilei Wang ,  Tao Yang ,  Junfeng Li

IPC: H01L21/28 ,  H01L21/285 ,  C23C16/02 ,  C23C16/14 ,  C23C16/455 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/28562 ,  C23C16/0272 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/76876 ,  H01L21/76877 ,  H01L29/66545

Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.

Abstract translation: 公开了沉积钨（W）层的方法。 一方面，该方法包括在衬底的表面上沉积SiH 4基底W膜以预处理该表面。 该方法包括在预处理的表面上沉积B2H6基底W层。 SiH4基底W膜可以是几个原子层厚。 膜和基底W层可以沉积在单个ALD工艺中，包括反应气体浸泡，反应气体引入和主沉积操作。 形成膜可以包括在气体浸泡操作期间将SiH 4气体引入反应腔中，并且在气体引入操作期间将SiH 4和WF 6气体引入空腔。 SiH4和WF6气体可以根据待沉积的钨层的厚度交替地引入多个循环。

公开(公告)号：US10096691B2

公开(公告)日：2018-10-09

申请号：US14812490

申请日：2015-07-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qingzhu Zhang ,  Lichuan Zhao ,  Xiongkun Yang ,  Huaxiang Yin ,  Jiang Yan ,  Junfeng Li ,  Tao Yang ,  Jinbiao Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L29/417 ,  H01L21/28

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

公开(公告)号：US09590076B1

公开(公告)日：2017-03-07

申请号：US14402303

申请日：2014-08-01

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinbiao Liu ,  Yao Wang ,  Guilei Wang ,  Tao Yang ,  Qing Liu ,  Junfeng Li

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/785

Abstract: A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.

Abstract translation: 一种制造FinFET器件的方法，包括提供衬底; 在衬底上实现源极/漏极掺杂; 蚀刻掺杂衬底以形成源区和漏区; 在源极区域和漏极区域之间形成鳍状沟道; 并在Fin通道上形成一个门。 在源极/漏极掺杂在衬底上实现之后形成鳍和栅极，使得源极/漏极掺杂作为平面器件的掺杂进行，这确保了源/漏极应对的质量并提高了其性能 的FinFET器件。