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    Plastic film supported single crystal silicon photovoltaic cell structure and method of fabrication
    2.
    发明公开
    Plastic film supported single crystal silicon photovoltaic cell structure and method of fabrication 审中-公开
    通过由单晶硅和制造工艺的塑料薄膜光伏电池支持

    公开(公告)号：EP1659640A1

    公开(公告)日：2006-05-24

    申请号：EP04425867.1

    申请日：2004-11-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Montanini, Pietro ,  Riboli, Paolo ,  Zanotti, Luca ,  Palmieri, Michele ,  Mottura, Marta

    IPC: H01L31/18 ,  H01L31/068 ,  H01L21/762

    CPC classification number: H01L31/1804 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

    Abstract: A method of fabricating a wafer-size photovoltaic cell module capable of drastically reducing the overall costs of photovoltaic cells of enhanced efficiency realized on a monocrystalline silicon substrate comprises the steps of:

    defining an integrated cellular structure, of a light converting monolateral or bilateral junction diode in the epitaxially grown detachable layer, including a first deposited metal current collecting terminal of the diode;
    laminating onto the surface the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions;
    immersing the wafer in a hydrofluoric acid solution causing detachment of the processed epitaxially grown silicon layer laminated with the film of optical grade plastic material;
    polishing the surface of separation of the detached processed epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a relatively low temperature tolerable by the film of optical grade plastic material.

    Abstract translation: 制造能够大幅度地减少的实现上的单晶硅衬底增强效率的光伏电池的总成本的晶片尺寸太阳能电池组件的方法，包括以下步骤：光的集成蜂窝结构的 - 定义，转换单边或双边结二极管 在外延生长层可拆卸的，包括第一熔敷金属集流二极管的端子; 到表面上的处理外延生长可分离层层压的光学级塑料材料，以氢氟酸溶液腐蚀的膜; 浸渍在曹景伟层叠有光学级塑料材料制成的膜经处理的外延生长的硅层的剥离氢氟酸溶液的晶片; 抛光处理分离外延生长层的分离表面以及形成第二金属电流在相对低的温度下的光学级塑料材料制成的膜可容忍收集二极管通过金属的掩蔽沉积的终端。

    Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells
    3.
    发明授权
    Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells 失效
    一种用于制备具有高电压和低电压横向DMOS-技术功率器件和非易失性存储器单元intergrierten电路处理

    公开(公告)号：EP0731504B1

    公开(公告)日：2002-11-27

    申请号：EP95830088.1

    申请日：1995-03-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Contiero, Claudio ,  Galbiati, Paola ,  Palmieri, Michele

    IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/8247 ,  H01L21/265 ,  H01L27/06 ,  H01L29/78

    CPC classification number: H01L29/66659 ,  H01L21/823456 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0847 ,  H01L29/66674 ,  H01L29/7816

    Abstract: A process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells provides for: forming respective laterally displaced isolated semiconductor regions (R1,R2,R6), electrically insulated from each other and from a common semiconductor substrate (1), inside which the devices will be formed; forming conductive insulated gate regions (33,34,37) for the lateral DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions (R1,R2,R6); inside the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, forming deep body regions (25,26) aligned with edges of the insulated gate regions (33,34), and channel regions (29,30) extending under the insulated gate regions (33,34). The deep body regions (25,26) are formed by means of a first implantation of a first dopant in a direction substantially orthogonal to a top surface of the integrated circuit, performed with an energy and with a dopant dose such that the concentration of the first dopant has a peak located at a prescribed distance from the surface of the isolated semiconductor regions (R1,R2). The channel regions (29,30) are formed by means of a second implantation of a second dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that said channel regions (29,30) are formed directly after the implantation of the second dopant without performing a thermal diffusion at a high temperature of the second dopant.

    Integrated circuit with highly efficient junction insulation
    7.
    发明公开
    Integrated circuit with highly efficient junction insulation 失效
    Integrierte Schaltung mit hocheffizienter隔离性PN-Übergang

    公开(公告)号：EP0915508A1

    公开(公告)日：1999-05-12

    申请号：EP97830507.6

    申请日：1997-10-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pozzoni, Massimo ,  Galbiati, Maria Paola ,  Palmieri, Michele ,  Pedrazzini, Giorgio ,  Rossi, Domenico

    IPC: H01L21/761

    CPC classification number: H01L21/761

    Abstract: There is described an integrated circuit with junction insulation on a substrate (10) of semiconductor material comprising active regions (11, 11', 11'') of a first type of conductivity (n), insulation regions (30-33) which separate the junction-forming active regions from one another and from the substrate and means of electrical contact for reverse-biasing the junctions. In order to obtain highly efficient insulation, at least one (11) of the active regions is separated from the active regions adjacent to it (11') and from the substrate (10) by insulation regions (30-33) which form an inner insulation shell, consisting of regions (30, 31) of conductivity of a second type (p), opposite to the first type, which contains the active region (11) and an outer insulation shell, consisting of regions (32, 33) of the first type of conductivity (n) which contains the inner insulation shell.

    Abstract translation: 描述了在半导体材料的衬底（10）上具有结绝缘的集成电路，其包括第一类型导电（n）的有源区（11,11'，11“），绝缘区（30-33），其分离 所述接合形成有源区彼此和所述衬底以及用于反向偏置所述接点的电接触装置。 为了获得高效绝缘，通过绝缘区域（30-33）将至少一个有源区域与其邻近的有源区（11'）和基板（10）分离，形成内部 绝缘壳体，包括与第一类型相反的第二类型（p）的导电性的区域（30,31），所述第一类型包含有源区域（11）和外部绝缘壳体，所述外部绝缘壳体由以下区域（32,33）组成： 第一种导电性（n）包含内绝缘壳。

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