公开(公告)号：KR20180065855A

公开(公告)日：2018-06-18

申请号：KR20170059092

申请日：2017-05-12

Applicant: 한양대학교 산학협력단

Inventor： PARK SANG GYU ,  CHO IN HWAN

IPC: H03M3/00

CPC classification number: H03M3/372 ,  H03M3/39 ,  H03M2201/64

Abstract: 피크전류를낮추면서도 1 phase 내에모든방전을수행할수 있는디지털아날로그컨버터및 이의동작방법이개시된다. 상기디지털아날로그컨버터는증폭기, 상기증폭기의입력단중 하나에연결된충전소자및 상기충전소자의충전전압을제 1 방전구간및 제 2 방전구간으로구분하여방전시키는방전제어부를포함한다. 여기서, 상기제 1 방전구간에서의시상수가상기제 2 방전구간에서의시상수보다크다.

公开(公告)号：KR1020000073026A

公开(公告)日：2000-12-05

申请号：KR1019990016043

申请日：1999-05-04

Applicant: 삼성전자주식회사

Inventor： 강근순

IPC: H03M1/34

CPC classification number: H03M1/34 ,  H03M1/08 ,  H03M2201/64

Abstract: PURPOSE: A latch comparator of an analog-digital converter is provided, which reduces variations in voltages of the drains of MOS transistors constituting a switch circuit to decrease noise generated due to variations in the voltages between the drains and gates of the MOS transistors. CONSTITUTION: A latch comparator of an analog-digital converter includes a comparator, a control signal generator and a latch comparator. The latch comparator(300) has an output driving circuit(310), a switch circuit(320) and a discharge circuit(330). The output driving circuit maintains the voltages of output ports at the same level under the control of a first control signal from the control signal generator during a reset operation and outputs complementary first and second digital signals according to a switching result of the switch circuit during a comparison operation. The switch circuit includes first and second MOS transistors and transmits charges from the output driving circuit to the discharge circuit under the control of first and second analog signals from the comparator. The discharge circuit discharges the charges to ground voltage during the reset and comparison operations under the control of the first and second control signals.

Abstract translation: 目的：提供模数转换器的锁存比较器，其减小构成开关电路的MOS晶体管的漏极的电压变化，以降低由于MOS晶体管的漏极和栅极之间的电压变化而产生的噪声。 构成：模拟数字转换器的锁存比较器包括比较器，控制信号发生器和锁存比较器。 锁存比较器（300）具有输出驱动电路（310），开关电路（320）和放电电路（330）。 输出驱动电路在复位操作期间，在来自控制信号发生器的第一控制信号的控制下，将输出端口的电压维持在相同的电平，并根据开关电路的切换结果输出互补的第一和第二数字信号 比较操作。 开关电路包括第一和第二MOS晶体管，并且在来自比较器的第一和第二模拟信号的控制下将电荷从输出驱动电路传输到放电电路。 在第一和第二控制信号的控制下，放电电路在复位和比较操作期间将电荷放电至接地电压。

公开(公告)号：KR1020000019778A

公开(公告)日：2000-04-15

申请号：KR1019980038048

申请日：1998-09-15

Applicant: 삼성전자주식회사

Inventor： 조용진

IPC: H03M1/66

CPC classification number: H03M1/76 ,  H03M2201/64

Abstract: PURPOSE: A digital-analog converter is provided to prevent a distortion of an output analog waveform by compensating an on-resistance of switches comprised in the converter. CONSTITUTION: A digital-analog converter comprises a selector(100) having n switches and a voltage dividing part(200). The selector(100) selects either or of a lower reference voltage via a lower reference voltage terminal(Vrefl) and an upper reference voltage via an upper reference voltage terminal(Vrefh), in response to a data signal(B0-B11) from the exterior. The voltage dividing part(200) divides voltages transferred via the switches(S0-S11) of the selector, respectively, and has a first resistor string(220) and a second resistor string(240). The first resistor string has first n resistors coupled in serial between the lower reference voltage terminal and an output terminal(Vout) for outputting the divided voltage. The first resistors(220) have a resistance value corresponding to a sum of half an on-resistance of each switch and a resistance of R. The second resistor string(240) has second n resistors coupled in parallel between the output terminal and the first resistors and between the switches, and the second resistors have a resistance of 2R.

Abstract translation: 目的：提供数模转换器，通过补偿转换器中包含的开关导通电阻来防止输出模拟波形失真。 构成：数模转换器包括具有n个开关和分压部分（200）的选择器（100）。 响应于来自所述选择器（100）的数据信号（B0-B11），所述选择器（100）经由较低参考电压端子（Vrefl）和较高参考电压经由上参考电压端子（Vrefh）选择或者较低参考电压 外观。 分压部分（200）分别分别经由选择器的开关（S0-S11）传送的电压，并具有第一电阻串（220）和第二电阻串（240）。 第一电阻串具有串联连接在下参考电压端与输出端之间的前n个电阻（Vout），用于输出分压。 第一电阻器（220）具有对应于每个开关的导通电阻的一半和R的电阻的和的电阻值。第二电阻器串（240）具有并联在输出端子和第一电阻器 电阻器和开关之间，并且第二电阻器具有2R的电阻。

公开(公告)号：KR1020110108564A

公开(公告)日：2011-10-06

申请号：KR1020100027826

申请日：2010-03-29

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  권이기 ,  김차동

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M7/165 ,  H03M2201/62 ,  H03M2201/64 ,  H03M2201/932

Abstract: 본 발명은 전류구동방식의 DAC에 관한 것으로서, MSB에 대응하는 제 1 CCA, ISB에 대응하는 제 2 CCA, LSB에 대응하는 제 3 CCA, 및 제 1 CCA, 제 2 CCA, 그리고 제 3 CCA 각각에 상호 독립적인 기준 전류를 공급하는 CSA를 포함하고, MSB와 ISB는 온도계 코드, LSB는 이진 가중치 코드로 구성하는 것을 특징으로 하며, 전류 셀의 크기를 줄임으로써, 전체 칩 면적을 줄일 수 있으며, 기생 커패시터 성분에 의한 고속 동작에서의 성능저하를 막을 수 있다.

公开(公告)号：KR20100085322A

公开(公告)日：2010-07-29

申请号：KR20090004534

申请日：2009-01-20

Applicant: IUCF HYU

Inventor： YOO CHANG SIK ,  JO JUN GI ,  CHOI WOO SEOK

IPC: H03M3/02

CPC classification number: H03M3/39 ,  H01L27/0922 ,  H03M2201/61 ,  H03M2201/64

Abstract: PURPOSE: The continuous-time sigma-delta modulator can reduce the burden which has to increase the peak value of on current by being proceed the charging operation or the electric discharge operation with the capacitors of 2 through one cycle whole. CONSTITUTION: An integrator(200) integrates the difference of the analog signal and the differential-inputted input signal. The analog to digital convertor(220) changes the output of integrator into the digital output signal. The digital analog converter(240) changes the digital output signal into the analog signal. In the first switching route is the discharge section, the analog signal corresponding to the digital output signal is generated. In the first switching route is the filled sphere liver, the reference voltage is stored.

Abstract translation: 目的：连续时间Σ-Δ调制器可以减少负载，通过进行充电操作或放电操作，电容器2通过一个周期整体，增加电流峰值。 构成：积分器（200）集成了模拟信号和差分输入信号的差异。 模数转换器（220）将积分器的输出变为数字输出信号。 数字模拟转换器（240）将数字输出信号改变成模拟信号。 在第一开关路径中为放电部，产生与数字输出信号对应的模拟信号。 在第一个切换路线是充满球体的肝脏，参考电压被存储。

公开(公告)号：KR1020050081044A

公开(公告)日：2005-08-18

申请号：KR1020040009283

申请日：2004-02-12

Applicant: 매그나칩 반도체 유한회사

Inventor： 오명규

IPC: H03M1/36

CPC classification number: H03M1/0607 ,  H03M1/12 ,  H03M2201/6107 ,  H03M2201/64 ,  H03M2201/83 ,  H03M2201/847

Abstract: 본 발명은 아날로그 디지털 컨버터에 관한 것으로서, 보다 상세하게는 칩 내부의 입력라인에 차지되어 있는 전하를 디스차지 또는 프리차지시켜, 입력라인의 전압과 아날로그 입력전압의 차이에 따른 노이즈 발생을 방지할 수 있도록 하는데 있다.
이를 위해, 본 발명은 복수개의 채널의 아날로그 입력전압을 선택적으로 출력하는 스위칭그룹과, 입력라인의 전위를 상기 아날로그 입력전압과 동전위로 프리차지시키는 프리차지수단과, 상기 프리차지수단에 의해 프리차지된 후에 구동되어 상기 아날로그 입력전압을 전달하는 인에이블수단과, 상기 인에이블수단으로부터 전달된 상기 아날로그 입력전압을 기준전압과 비교 증폭하여 출력하는 비교부를 포함하여 구성함을 특징으로 한다.

公开(公告)号：KR1020100041364A

公开(公告)日：2010-04-22

申请号：KR1020080100513

申请日：2008-10-14

Applicant: 엘지이노텍 주식회사

Inventor： 박청용

IPC: H03M1/66

CPC classification number: H03M1/362 ,  H03M2201/61 ,  H03M2201/64 ,  H03M2201/814

Abstract: PURPOSE: An A/D converter is provided to improve the distortion of a signal by using a transmission gate switch and reducing an offset voltage. CONSTITUTION: A reference voltage generating part(10) respectively outputs a plurality of reference voltage signals which are generated at a resistor string with a plurality of resistor. A plurality of transmission gate switches(40) receives each reference voltage signal from the reference voltage generating part. The transmission gate switch maintains the state of the reference voltage signal without the offset voltage change. A plurality of comparators(20) respectively outputs 0 or 1 by comparing the input signal of the unit pixel and a reference voltage signal. An encoding unit(30) outputs the digital signal of N bit by encoding the output from the comparator.

Abstract translation: 目的：提供A / D转换器，通过使用传输门极开关并降低偏移电压来改善信号的失真。 构成：参考电压产生部分（10）分别输出在电阻器串上产生的多个参考电压信号与多个电阻器。 多个传输门开关（40）从参考电压产生部分接收每个参考电压信号。 传输门开关保持参考电压信号的状态，而不会发生偏移电压变化。 多个比较器（20）通过比较单位像素的输入信号和参考电压信号分别输出0或1。 编码单元（30）通过对比较器的输出进行编码来输出N位的数字信号。

公开(公告)号：KR1020080007713A

公开(公告)日：2008-01-23

申请号：KR1020060066686

申请日：2006-07-18

Applicant: 고려대학교 산학협력단

Inventor： 손종필 ,  김수원

IPC: H03M1/12

CPC classification number: H03M1/0621 ,  H03M1/1265 ,  H03M2201/11 ,  H03M2201/6121 ,  H03M2201/64

Abstract: An analog to digital converter with a variable sampling period according to a noise level, and an audio recorder and a pacemaker using the same are provided to maintain an SNR(Signal to Noise Ratio) uniformly and to minimize power consumption by reducing the sampling period in the environment with low noise and increasing the sampling period in the environment with high noise. An analog to digital converter with a variable sampling period according to a noise level includes an analog to digital converting unit(110), a noise detecting unit(120), and a clock selecting unit(130). The analog to digital converting unit converts an analog input signal to a digital signal. The noise detecting unit detects the noise ingredients of the digital signal. The clock selecting unit selects one among a plurality of different clock signals according to the noise ingredients and applies the selected clock to the clock input of the analog to digital converting unit.

Abstract translation: 提供具有根据噪声电平的可变采样周期的模数转换器，以及使用该数字转换器的音频记录器和起搏器，以均匀地维持SNR（信噪比），并通过减少采样周期来最小化功耗 环境噪声低，环境噪声高的采样周期增加。 根据噪声电平具有可变采样周期的模数转换器包括模数转换单元（110），噪声检测单元（120）和时钟选择单元（130）。 模数转换单元将模拟输入信号转换为数字信号。 噪声检测单元检测数字信号的噪声成分。 时钟选择单元根据噪声成分选择多个不同时钟信号中的一个，并将所选择的时钟施加到模数转换单元的时钟输入端。

公开(公告)号：KR1020020000608A

公开(公告)日：2002-01-05

申请号：KR1020000035404

申请日：2000-06-26

Applicant: 삼성전자주식회사

Inventor： 이영준 ,  이승권

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/64 ,  H03M2201/932

Abstract: PURPOSE: A digital/analog converter circuit with an input buffer circuit is provided to output a signal having a desired noise characteristic by using an input buffer circuit for controlling an input signal and a simple RC filter. CONSTITUTION: An input buffer circuit(10) is synchronized with a low sampling frequency in order to receive digital input data and a multitude of signal from the outside. The input buffer circuit(10) is synchronized with a high sampling frequency in order to output the digital input data to a digital/analog converter(20). The digital/analog converter(20) receives the digital data from the input buffer circuit(10) and outputs analog signals. An RC filter circuit(30) receives the analog signal from the digital/analog converter(20) and filters frequencies of a low band to reduce noise.

Abstract translation: 目的：提供具有输入缓冲电路的数字/模拟转换器电路，通过使用用于控制输入信号的输入缓冲电路和简单的RC滤波器来输出具有期望噪声特性的信号。 构成：输入缓冲电路（10）与低采样频率同步，以便从外部接收数字输入数据和大量信号。 输入缓冲电路（10）与高采样频率同步，以将数字输入数据输出到数/模转换器（20）。 数字/模拟转换器（20）从输入缓冲电路（10）接收数字数据并输出模拟信号。 RC滤波器电路（30）从数/模转换器（20）接收模拟信号，并对低频带的频率进行滤波以减少噪声。

公开(公告)号：KR1020000044683A

公开(公告)日：2000-07-15

申请号：KR1019980061182

申请日：1998-12-30

Applicant: 에스케이하이닉스 주식회사

Inventor： 임지수

IPC: H03M1/40

CPC classification number: H03M1/0818 ,  H03M1/0607 ,  H03M1/38 ,  H03M2201/64

Abstract: PURPOSE: An analog-to-digital converter of a successive approximation type is provided to mitigate an offset and an affect owing to a clock feedthrough. CONSTITUTION: An analog-to-digital converter of a successive approximation type comprises an input stage(208) which samples and holds an analog input signal from the exterior. A digital-to-analog converter(202) is connected between a positive reference voltage(Vref+) and a negative reference voltage(Vref-), and generates an analog comparison signal corresponding to a digital code from a successive approximation register(SAR). A reference voltage generator(212) samples and holds a voltage corresponding to half the reference voltage(Vref+). A switch(214) is connected between the digital-to-analog converter(202) and an input terminal of a comparator(204) and is controlled by a hold signal(hold) from a SAR logic(206) so as to transfer an analog comparison signal to the input terminal of the comparator(204). The comparator(204) receives the sampled input signal of the input stage(208), the reference voltage(Vref/2) of the reference voltage generator(212), and the analog comparison signal transferred through the switch(214). The comparator(204) compares the sampled input signal or the analog comparison signal with the reference voltage, and outputs a high level through a positive output when the sampled input signal or the analog comparison signal is higher than the reference voltage. The comparator(204) outputs a low level through the positive output when both the sampled input signal and the analog comparison signal are less than the reference voltage. The SAR logic(206) receives an output of the comparator(204) through a latch(210), and generates a digital code value of the inputted analog signal.

Abstract translation: 目的：提供逐次逼近型的模数转换器，以减轻由于时钟馈通导致的偏移和影响。 构成：逐次逼近型的模拟 - 数字转换器包括从外部采样和保持模拟输入信号的输入级（208）。 数模转换器（202）连接在正参考电压（Vref +）和负参考电压（Vref-）之间，并产生与来自逐次逼近寄存器（SAR）的数字代码对应的模拟比较信号。 参考电压发生器（212）对与基准电压（Vref +）的一半相对应的电压进行采样和保持。 开关（214）连接在数/模转换器（202）和比较器（204）的输入端之间，由SAR逻辑（206）的保持信号（保持）控制，以便传送 模拟比较信号到比较器（204）的输入端。 比较器（204）接收输入级（208）的采样输入信号，参考电压发生器（212）的参考电压（Vref / 2）和通过开关（214）传送的模拟比较信号。 比较器（204）将采样输入信号或模拟比较信号与参考电压进行比较，当采样输入信号或模拟比较信号高于参考电压时，通过正输出输出高电平。 当采样输入信号和模拟比较信号均小于参考电压时，比较器（204）通过正输出输出低电平。 SAR逻辑（206）通过锁存器（210）接收比较器（204）的输出，并产生输入的模拟信号的数字码值。