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公开(公告)号：KR1020040053486A
公开(公告)日：2004-06-24
申请号：KR1020020080045
申请日：2002-12-14
Applicant: 한국전자통신연구원
IPC: H03F3/45
Abstract: PURPOSE: A transimpedance amplifier for high-speed optical receiver is provided to enlarge a frequency band and lower the loss of the input/output reflection by performing an amplifying process twice and feeding back the amplified signal. CONSTITUTION: A transimpedance amplifier for high-speed optical receiver includes the first amplifier, the second amplifier, a feedback circuit, and a buffer. The first amplifier(110) is used for converting an optical current to a voltage and amplifying the converted voltage. The second amplifier(120) is used for amplifying an output of the first amplifier. The feedback circuit(130) feeds back an output of the second amplifier to the first amplifier. The buffer(140) buffers an output signal of the feedback circuit.
Abstract translation: 目的：提供一种用于高速光接收机的跨阻放大器，通过进行两次放大处理并反馈放大信号来放大频带并降低输入/输出反射损耗。 构成：用于高速光接收器的跨阻放大器包括第一放大器，第二放大器，反馈电路和缓冲器。 第一放大器（110）用于将光电流转换成电压并放大转换的电压。 第二放大器（120）用于放大第一放大器的输出。 反馈电路（130）将第二放大器的输出反馈到第一放大器。 缓冲器（140）缓冲反馈电路的输出信号。
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公开(公告)号：KR1020040043282A
公开(公告)日：2004-05-24
申请号：KR1020020071501
申请日：2002-11-18
Applicant: 한국전자통신연구원
IPC: G02B6/12
Abstract: PURPOSE: A submount for electro optical device of a high speed electro optical module is provided to reduce the transmission loss and the reflection loss of the data by drastically reducing the parasitic effect remained at the peripheral of the wire bonding. CONSTITUTION: A submount for electro optical device of a high speed electro optical module includes a dielectric material(20), a pair of ground lines(22a,22c), a signal line(22b), a bias line(22d), a ground plane(28) and a via hole. The dielectric material(20) is in the shape of "L". The pair of ground lines(22a,22c), the signal line(22b) and the bias line(22d) are stacked on the top surface of the dielectric material(20) by using a co-planar waveguide-ground(CPW-G). The ground plane(28) is positioned inside of the dielectric material(20). And, the via hole is connected the ground lines(22a,22c) to the ground plane(28).
Abstract translation: 目的：提供高速电光模块的电子光学装置的底座，通过大大减少引线键合周边残留的寄生效应，减少数据的传输损耗和反射损耗。 构成：高速电光模块的电光装置用基座包括电介质材料（20），一对接地线（22a，22c），信号线（22b），偏置线（22d），接地 平面（28）和通孔。 电介质材料（20）为“L”形。 该一对接地线（22a，22c），信号线（22b）和偏置线（22d）通过使用共面波导 - 接地（CPW-G）堆叠在电介质材料（20）的顶表面上 ）。 接地平面（28）位于电介质材料（20）的内部。 并且，通孔将接地线（22a，22c）连接到接地平面（28）。
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公开(公告)号：KR100396917B1
公开(公告)日：2003-09-02
申请号：KR1020000079748
申请日：2000-12-21
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: PURPOSE: A fabrication method of an integrated circuit is provided to efficiently reduce a chip size by using a defined epitaxial layer of an HBT(Heterojunction Bipolar Transistor) as a resistor having a large resistance and using another defined epitaxial layer as a stabilizing resistor. CONSTITUTION: After removing an emitter cap layer(9), an emitter layer, and a surface of a base layer, base metal electrodes(11) is formed on both sides of an emitter metal electrode(10). After etching the base layer, a collector layer, and a surface of a second selective etch layer, the second selective etch layer is selectively etched compared to a subcollector layer. The entire subcollector layer is removed except for an active device part included region and a lowly resistive resistor(14) region. Collector metal electrodes(12) are formed on the active device part included region, the lowly resistive resistor(14), and defined regions of a second selective etch layer(3) having a high resistance. Then, the second selective etch layer(3) is selectively removed and a partial etching step is performed for isolation between the active and passive devices.
Abstract translation: 目的：提供集成电路的制造方法，以通过使用HBT（异质结双极晶体管）的限定的外延层作为具有大电阻的电阻器并使用另一定义的外延层作为稳定电阻器来有效地减小芯片尺寸。 构成：在去除发射极覆盖层（9），发射极层和基极层的表面之后，在发射极金属电极（10）的两侧形成基极金属电极（11）。 在蚀刻基极层，集电极层和第二选择性蚀刻层的表面之后，与子集电极层相比，选择性蚀刻第二选择性蚀刻层。 除了有源器件部分包括区域和低电阻电阻器（14）区域之外，整个子集电极层被去除。 集电极金属电极（12）形成在包括有源器件部分的区域，低电阻电阻器（14）以及具有高电阻的第二选择性蚀刻层（3）的限定区域上。 然后，选择性地去除第二选择性蚀刻层（3），并执行局部蚀刻步骤以在有源和无源器件之间进行隔离。
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公开(公告)号：KR1020030042791A
公开(公告)日：2003-06-02
申请号：KR1020010073570
申请日：2001-11-24
Applicant: 한국전자통신연구원
IPC: G02B6/42
CPC classification number: G02B6/4201 , G02B6/4274 , G02B6/4279 , H01L2224/48091 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
Abstract: PURPOSE: A sub mount for photoelectric module and a mounting method using the same are provided to enhance an electrical characteristic by using a signal connection line of a co-planar waveguide structure. CONSTITUTION: A sub mount(200) for converting an incident ray of a photoelectric element(230) to an electric signal includes a dielectric(210) and a signal connection line(220). The dielectric has a front side(211) and a bottom side(212). The signal connection line is adhered on the front side and the bottom side. The signal connection line is electrically connected with the photoelectric element in order to output the electric signal from the photoelectric element. The signal connection line having a co-planar waveguide structure includes a plurality of signal connection lines. The plural signal connection lines include the first ground line(221), a signal transmission line(222), the second ground line(223), and a bias application line(224).
Abstract translation: 目的：提供一种用于光电模块的辅助安装座及其安装方法，以通过使用共面波导结构的信号连接线来增强电气特性。 构成：用于将光电元件（230）的入射光线转换为电信号的副安装座（200）包括电介质（210）和信号连接线（220）。 电介质具有前侧（211）和底侧（212）。 信号连接线粘附在前侧和底侧。 信号连接线与光电元件电连接，以便从光电元件输出电信号。 具有共平面波导结构的信号连接线包括多个信号连接线。 多个信号连接线包括第一接地线（221），信号传输线（222），第二接地线（223）和偏置施加线（224）。
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公开(公告)号：KR1020020050572A
公开(公告)日：2002-06-27
申请号：KR1020000079748
申请日：2000-12-21
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: PURPOSE: A fabrication method of an integrated circuit is provided to efficiently reduce a chip size by using a defined epitaxial layer of an HBT(Heterojunction Bipolar Transistor) as a resistor having a large resistance and using another defined epitaxial layer as a stabilizing resistor. CONSTITUTION: After removing an emitter cap layer(9), an emitter layer, and a surface of a base layer, base metal electrodes(11) is formed on both sides of an emitter metal electrode(10). After etching the base layer, a collector layer, and a surface of a second selective etch layer, the second selective etch layer is selectively etched compared to a subcollector layer. The entire subcollector layer is removed except for an active device part included region and a lowly resistive resistor(14) region. Collector metal electrodes(12) are formed on the active device part included region, the lowly resistive resistor(14), and defined regions of a second selective etch layer(3) having a high resistance. Then, the second selective etch layer(3) is selectively removed and a partial etching step is performed for isolation between the active and passive devices.
Abstract translation: 目的：提供集成电路的制造方法，通过使用HBT（异质结双极晶体管）的限定外延层作为具有大电阻的电阻并使用另一限定的外延层作为稳定电阻来有效降低芯片尺寸。 构成：在发射极金属电极（10）的两侧形成有发射极覆盖层（9），发射极层和基极层的表面之后的基底金属电极（11）。 在蚀刻基底层，集电极层和第二选择性蚀刻层的表面之后，与子集电极层相比，选择性地蚀刻第二选择性蚀刻层。 除了有源器件部件包含区域和低电阻电阻器（14）区域之外，除去整个子集电极层。 集电极金属电极（12）形成在有源器件部分包含的区域，低电阻电阻（14）和具有高电阻的第二选择蚀刻层（3）的限定区域中。 然后，选择性地去除第二选择性蚀刻层（3），并且执行部分蚀刻步骤以在有源和无源器件之间进行隔离。
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Patent Agency Ranking
公开(公告)号：KR102219400B1
公开(公告)日：2021-02-26
申请号：KR1020150120212
申请日：2015-08-26
Applicant: 한국전자통신연구원
Abstract: 반도체채널저항의등가회로를구성하는방법은, 반도체채널저항의제 1 전극및 제 2 전극을정의하는단계, 상기제 1 전극및 상기제 2 전극사이에연결되는수동소자부를정의하는단계및 상기수동소자부내 상기적어도두 개의수동소자의파라미터값을각각결정하는단계를포함한다. 여기에서, 상기수동소자부는병렬연결된적어도두 개의수동소자를포함한다. 따라서, 주파수변화에도불구하고반도체채널저항의특성을정확히나타낼수 있다.
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公开(公告)号：KR101848244B1
公开(公告)日：2018-05-29
申请号：KR1020110133715
申请日：2011-12-13
Applicant: 한국전자통신연구원
IPC: H01L21/338 , H01L29/812
CPC classification number: H01L29/0649 , H01L21/28593 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
Abstract: 본발명은계단형게이트전극을포함하는반도체소자및 그제조방법에관한것이다. 본발명의일 실시예에의한반도체소자의제조방법은, 다수의에피택셜층(epitaxial layer) 구조의반도체기판상에캡층(cap layer)을형성하고상기캡층의일부를식각하여활성영역을형성하는단계, 상기활성영역과상기캡층상에제 1 질화막, 제 2 질화막및 게이트형성을위한레지스트패턴을순차적으로형성하는단계, 상기레지스트패턴을통해상기제 2 질화막과상기제 1 질화막을순차적으로식각하고상기레지스트패턴을제거하여계단형의게이트절연막패턴을형성하는단계, 상기제 2 질화막상에게이트헤드패턴을형성하는단계, 상기게이트절연막패턴을통해상기반도체기판최상부의쇼트키층일부를식각하여언더컷(under-cut) 영역을형성하는단계, 상기게이트절연막패턴과상기게이트헤드패턴을통해내열성금속을증착하여계단형의게이트전극을형성하는단계및 상기게이트헤드패턴을제거하고절연막을증착하는단계를포함한다.
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公开(公告)号：KR101846388B1
公开(公告)日：2018-04-09
申请号：KR1020110125763
申请日：2011-11-29
Applicant: 한국전자통신연구원
IPC: H01L27/02 , H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L23/481 , H01L28/92 , H01L2924/0002 , H01L2924/00
Abstract: 본발명은수직구조캐패시터및 수직구조캐패시터의형성방법에관한것이다. 수직구조캐패시터는반도체기판의상부면에입력전극과출력전극을형성하고반도체기판의하부면을식각하여비아전극들을형성한후 상기비아전극들사이에유전체막을형성하여수직구조캐패시터가기판내에형성된다. 본발명에의하면수직구조캐패시터는적은면적에큰 용량의캐패시턴스를갖는캐패시터를제작할수 있다.
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公开(公告)号：KR1020170106576A
公开(公告)日：2017-09-21
申请号：KR1020160029526
申请日：2016-03-11
Applicant: 한국전자통신연구원
CPC classification number: H01L2224/49175
Abstract: 본발명은전력소자가구비된기판에관한것이다. 본발명에따르면, 한쌍의제1 마커및 한쌍의제2 마커가형성된메탈캐리어, 상기메탈캐리어상에구비되며, 입력단이상기한 쌍의제1 마커중 어느하나에대응되고, 출력단이상기한 쌍의제1 마커중 나머지하나에대응되도록배치되는전력소자, 상기전력소자의일 측에배치되는입력정합부및 상기전력소자의타 측에배치되는출력정합부를포함하며, 상기한 쌍의제2 마커는상기한 쌍의제1 마커의외측에형성되고, 상기입력정합부의일 측면은상기제2 마커중 어느하나에대응되도록배치되며, 상기출력정합부의일 측면은상기제2 마커중 나머지하나에대응되도록배치되는, 전력소자가구비된기판이제공된다.
Abstract translation: 具有电源的基板技术领域本发明涉及一种设有电源的基板。 根据本发明，一对第一标记物和一对金属载体2，一标记形成时，它被设置在所述金属载体上，该输入级移相器对第一标记中的一个的相应的一个，输出移相器对第一 并且输出匹配部分设置在电源的另一侧上，其中该对第二标记布置在电源的另一侧上， 其中，所述输入匹配单元的一侧对应于所述第二标记中的一个，所述输出匹配单元的一侧对应于所述第二标记中的另一个， 提供衬底。
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