公开(公告)号：AT504078T

公开(公告)日：2011-04-15

申请号：AT04780054

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

公开(公告)号：AT487234T

公开(公告)日：2010-11-15

申请号：AT05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

公开(公告)号：AT453927T

公开(公告)日：2010-01-15

申请号：AT06793952

申请日：2006-10-03

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L21/762

Abstract: A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.

公开(公告)号：DE60223419T2

公开(公告)日：2008-09-04

申请号：DE60223419

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786