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    METHOD FOR FORMING A RELEASED MICROSTRUCTURE SUITABLE FOR A MICROELECTROMECHANICAL DEVICE
    91.
    发明申请
    METHOD FOR FORMING A RELEASED MICROSTRUCTURE SUITABLE FOR A MICROELECTROMECHANICAL DEVICE 审中-公开
    形成适用于微电子设备的释放微结构的方法

    公开(公告)号：WO2003104141A1

    公开(公告)日：2003-12-18

    申请号：PCT/SG2003/000141

    申请日：2003-06-10

    Applicant: INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING ,  TANG, Xiaosong ,  CHUA, Bee, Lee ,  LI, Zhihong ,  NORMAN, C. Tien ,  TAY, Eng Hock, Francis

    Inventor： TANG, Xiaosong ,  CHUA, Bee, Lee ,  LI, Zhihong ,  NORMAN, C. Tien ,  TAY, Eng Hock, Francis

    IPC: B81C1/00

    CPC classification number: B81C1/00936 ,  B81C2201/014

    Abstract: A MEMS device is formed from a silicon device layer (9), an intermediate thermal oxide layer (7), and a silicon substrate (5). A microstructure is formed by a removal of material from the device layer (9), where the intermediate layer (7) is resistant to the removal technique, eg, acting as an etch stop layer. The microstructure is released by selective removal of portions of the substrate layer (9) immediately below the microstructure, eg, via a backside etch, followed by removing portions of the intermediate layer (7) beneath the microstructure. Siction is avoided as there is no substrate below the microstructure.

    Abstract translation: MEMS器件由硅器件层（9），中间热氧化物层（7）和硅衬底（5）形成。 通过从器件层（9）去除材料形成微结构，其中中间层（7）对除去技术是有抵抗力的，例如用作蚀刻停止层。 通过选择性地去除微结构下方的基底层（9）的部分，例如经由背面蚀刻，随后除去微结构下面的中间层（7）的部分，来释放微结构。 避免了微观结构下面的底物。

    METHOD FOR MICROFABRICATING STRUCTURES USING SILICON-ON-INSULATOR MATERIAL
    93.
    发明申请
    METHOD FOR MICROFABRICATING STRUCTURES USING SILICON-ON-INSULATOR MATERIAL 审中-公开
    使用硅绝缘材料微结构的方法

    公开(公告)号：WO02054475A1

    公开(公告)日：2002-07-11

    申请号：PCT/US2002000015

    申请日：2002-07-11

    IPC: B81C1/00 ,  H01L21/46 ,  C23F1/00

    CPC classification number: B81C1/00119 ,  B81B2201/0235 ,  B81C1/00357 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2201/0191

    Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI). One first obtains an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.

    Abstract translation: 本发明提供了使用绝缘体上硅（SOI）制造微电子机械系统（MEMS）和相关器件的一般制造方法。 首先获得具有（i）手柄层，（ii）介电层和（iii）器件层）的SOI晶片。 已经在SOI晶片的器件层上进行了台面蚀刻，并且在SOI晶片的电介质层上进行了结构蚀刻。 然后，获得衬底（例如玻璃或硅），其中已将图案蚀刻到衬底上。 SOI晶片和衬底结合在一起。 然后去除SOI晶片的手柄层，随后是SOI晶片的电介质层。

    CMOS-COMPATIBLE MEM SWITCHES AND METHOD OF MAKING
    94.
    发明申请
    CMOS-COMPATIBLE MEM SWITCHES AND METHOD OF MAKING 审中-公开
    CMOS兼容元件开关及其制造方法

    公开(公告)号：WO0135433A3

    公开(公告)日：2001-12-27

    申请号：PCT/US0023197

    申请日：2000-08-23

    Applicant: HRL LAB LLC

    Inventor： CHOW LAP-WAI ,  HSU TSUNG-YUAN ,  HYMAN DANIEL J ,  LOO ROBERT Y ,  OUYANG PAUL ,  SCHAFFNER JAMES H ,  SCHMITZ ADELE ,  SCHWARTZ ROBERT N

    IPC: B81B3/00 ,  B81C1/00 ,  H01H1/021 ,  H01H1/58 ,  H01H49/00 ,  H01H59/00 ,  H01H50/00

    CPC classification number: B81C1/00246 ,  B81B2201/014 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735 ,  H01H1/58 ,  H01H59/0009 ,  H01H2001/0057

    Abstract: A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as viasto connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude towards each other. Thus, when the contacts are moved towards each other by actuating the MEM switch, they connect firmly without obstruction. Tungsten is typically used to form vias in CMOS processes, and it makes an excellent contact material, but other via metals may also be employed as contacts. Interconnect metallization may be employed for other structural and interconnect needs of the MEM switch, and is preferably standard for the foundry and process used. Various metals and dielectric materials may be used to create the switches, but in a preferred embodiment the interconnect metal layers are aluminum and the dielectric material is SiO2, materials which are fully compatible with standard four-layer CMOS fabrication processes.

    Abstract translation: 通过使用标准制造多个金属层集成电路（如CMOS）的处理步骤，廉价地制造了微机电（MEM）开关。 可以将精确的步骤调整为与特定代工厂的过程兼容，从而导致低成本且易于与其他电路集成的装置。 处理步骤包括从通常用作通过电介质层分离的永久连接的金属层的金属插头形成用于MEM开关的触点。 这种接触通孔形成在牺牲金属化区域的任一侧，然后从接触通孔之间移除互连金属化，使它们分开。 围绕触点的介质被回蚀，使得它们彼此突出。 因此，当通过致动MEM开关使触点彼此移动时，它们牢固地连接而不阻塞。 钨通常用于在CMOS工艺中形成通孔，并且它制成优良的接触材料，但也可以使用其它通孔金属作为接触。 互连金属化可以用于MEM开关的其他结构和互连需求，并且优选地是用于所使用的铸造和工艺的标准。 可以使用各种金属和介电材料来制造开关，但是在优选实施例中，互连金属层是铝，并且介电材料是SiO 2，与标准四层CMOS制造工艺完全兼容的材料。

    METHOD FOR PROCESSING SILICON USING ETCHING PROCESSES
    95.
    发明申请
    METHOD FOR PROCESSING SILICON USING ETCHING PROCESSES 审中-公开
    一种用于处理硅通过蚀刻工艺

    公开(公告)号：WO00023376A1

    公开(公告)日：2000-04-27

    申请号：PCT/DE1999/003018

    申请日：1999-09-22

    IPC: B81C1/00 ,  B81B3/00 ,  H01L21/302 ,  H01L21/3065

    CPC classification number: H01L21/30655 ,  B81C1/00571 ,  B81C2201/014

    Abstract: The invention relates to a method for etching a first silicon layer (15) which is provided with an etching mask (10) for defining lateral recesses (21). Trenches (21') are produced in the area of the lateral recesses (21) in a first plasma etching process by means of anisotropic etching. As soon as a barrier layer (12, 14, 14', 16) buried between the first silicon layer (15) and another silicon layer (17) is reached, the first etching process virtually comes to a stop (17). This barrier layer is then etched through in the exposed areas (23, 23') using a second etching process. An etching of the other silicon layer (17, 17') is then effected in a subsequent third etching process. This enables the production of free-standing structures for sensor elements using a simplified process which is fully compatible with the process steps in IC integration technology.

    Abstract translation: 建议用的蚀刻掩模（10），蚀刻第一硅层（15）来定义（21）设置在所述侧向凹槽的方法。 在第一种等离子体蚀刻工艺（21“）在横向凹槽（21）通过各向异性蚀刻沟槽的区域中产生的。 第一蚀刻工艺一旦一个第一硅层（15）和另外的硅层（17）之间埋入分离层（12，14，14”，16）实现来几乎停止。 此后，将该隔离层是在暴露部分（23，23“）通过第二蚀刻工艺蚀刻。 然后，随后的第三蚀刻工艺使硅层（17，17“）的一个进一步的蚀刻。 这个传感器元件的自由站立结构可以以简单的过程，是与IC集成技术的处理步骤完全兼容来制造。

    에칭방법 및 장치
    98.
    发明公开
    에칭방법 및 장치 有权
    에칭방법및장치

    公开(公告)号：KR1020070032965A

    公开(公告)日：2007-03-23

    申请号：KR1020067027668

    申请日：2005-06-23

    Applicant: 가부시키가이샤 아루박

    Inventor： 모리카와야스히로 ,  하야시도시오 ,  스우고우코우

    IPC: H01L21/3065

    CPC classification number: H01L21/30655 ,  B81C1/00595 ,  B81C2201/014 ,  H01J37/3255 ,  H01J2237/334

    Abstract: Etching method and system capable of deep etching with a large mask selection ratio and an excellent anisotropy. The etching system comprises a floating electrode sustained in potentially floating state while facing a substrate electrode provided in a vacuum chamber, a material for forming an etching protection film provided on the side of the floating electrode facing the substrate electrode, and a control means for applying high frequency power intermittently to the floating electrode. In the etching method, a sputter film is formed on the substrate by applying high frequency power to the floating electrode using the material for forming an etching protection film provided on the side facing the substrate electrode of the floating electrode disposed oppositely to the substrate electrode as a target material and using only rare gas as main gas. Subsequently, application of high frequency power to the floating electrode is interrupted, the substrate is etched by introducing etching gas into the vacuum chamber, and formation of the sputter film on the substrate and etching of the substrate are repeated according to a scheduled sequence (Fig. 1).

    Abstract translation: 蚀刻方法和系统能够以大的掩模选择比和优异的各向异性进行深度蚀刻。 该蚀刻系统包括：浮动电极，其面对设置在真空室中的衬底电极而可能处于浮动状态;用于形成蚀刻保护膜的材料，其设置在浮动电极的面向衬底电极的一侧;以及控制装置， 高频功率间歇地传送到浮动电极。 在该蚀刻方法中，通过使用设置在浮置电极的面向衬底电极的一侧上的用于形成蚀刻保护膜的材料向浮置电极施加高频电力，在衬底上形成溅射膜，所述浮置电极与衬底电极相对设置 目标材料和仅使用稀有气体作为主要气体。 随后，中断向浮动电极施加高频电力，通过向真空室中引入蚀刻气体来蚀刻衬底，并且根据预定顺序重复在衬底上形成溅射膜和蚀刻衬底（图5 1）。

    수직 단차 구조물의 제작 방법
    100.
    发明公开
    수직 단차 구조물의 제작 방법 失效
    用于制造垂直偏移结构的方法

    公开(公告)号：KR1020050111269A

    公开(公告)日：2005-11-24

    申请号：KR1020040036507

    申请日：2004-05-21

    Applicant: 삼성전자주식회사

    Inventor： 이상우 ,  김종팔 ,  이병렬

    IPC: B81C1/00

    CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/045 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G02B26/0841

    Abstract: 웨이퍼에 완전한 수직단차를 형성하는 수직 단차 구조물 제작 방법을 개시한다. 본 발명에 따른 수직 단차 구조물 제작 방법은 본 발명에 따른 수직 단차 구조물 제작 방법은 소정의 웨이퍼에 식각을 수행하여 제1 트렌치(trench)를 형성한 후, 제1 트렌치에 소정의 물질을 주입하는 제1 트렌치 형성 단계, 소정의 웨이퍼에 제1 박막을 증착하여 제2 및 제3 트렌치의 식각 위치를 결정하는 제1 패터닝(patterning)을 수행하고, 제1 박막 및 소정의 웨이퍼에 제2 박막을 증착하여 제3 트렌치의 식각 위치를 잠시 보호하는 제2 패터닝을 수행한 후, 소정의 웨이퍼에 식각을 수행하여 제2 트렌치를 형성하는 제1 식각 단계, 제2 트렌치의 측면에 보호막을 형성한 후, 소정의 웨이퍼에 식각을 수행하여 제2 트렌치를 수직 확장하는 제2 식각 단계, 제2 박막을 제거한 후 제2 박막이 제거된 위치에 식각을 수행하여 제3 트렌치를 형성하는 제3 식각 단계 및 소 정의 웨이퍼에 식각을 수행하여 제2 식각 단계에서 수직 확장된 제2 트렌치 및 제3 트렌치를 수평 확장하는 제4 식각 단계를 포함한다. 본 발명에 따르면, 구조물 사이의 수평간극이 보다 좁혀진다.

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