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91.发明授权
公开(公告)号：EP3173375B1
公开(公告)日：2018-11-14
申请号：EP16200506.0
申请日：2016-11-24
Inventor： PORNIN, Jean-Louis , BAILLIN, Xavier
IPC: B81C1/00
CPC classification number: B81C1/00333 , B81B2203/0315 , B81C1/00476 , B81C2201/013 , B81C2201/017 , B81C2201/056 , B81C2203/0136 , B81C2203/0145 , B81C2203/0154
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92.发明公开
公开(公告)号：EP3173375A1
公开(公告)日：2017-05-31
申请号：EP16200506.0
申请日：2016-11-24
Inventor： PORNIN, Jean-Louis , BAILLIN, Xavier
IPC: B81C1/00
CPC classification number: B81C1/00333 , B81B2203/0315 , B81C1/00476 , B81C2201/013 , B81C2201/017 , B81C2201/056 , B81C2203/0136 , B81C2203/0145 , B81C2203/0154
Abstract: Procédé d'encapsulation d'un dispositif microélectronique (100), comportant les étapes suivantes :
- réalisation d'une portion sacrificielle recouvrant le dispositif ;
- réalisation d'un capot (106) recouvrant la portion sacrificielle, comportant deux couches (108, 110) superposées de matériaux distincts et ayant des contraintes résiduelles et/ou des coefficients de dilatation thermique différents ;
- gravure, à travers le capot, d'une tranchée (112) dont le motif comporte une courbe et/ou deux segments droits non parallèles ;
- gravure de la portion sacrificielle à travers la tranchée ;
- dépôt d'un matériau de bouchage sur la tranchée ;
dans lequel, lors de la gravure de la portion sacrificielle, une portion (116) du capot définie par la tranchée se déforme sous l'effet d'une contrainte mécanique engendrée par les contraintes résiduelles et/ou une dilatation thermique des couches du capot et augmente les dimensions de la tranchée, cette contrainte étant supprimée avant le bouchage de la tranchée.-
公开(公告)号：EP2733114A4
公开(公告)日：2015-02-25
申请号：EP12815405
申请日：2012-07-10
Applicant: MURATA MANUFACTURING CO
Inventor： UMEDA KEIICHI
IPC: B81C1/00 , C23C14/02 , C23C14/16 , H01G4/33 , H01G5/16 , H03H3/02 , H03H3/04 , H03H9/02 , H03H9/13 , H03H9/17 , H03H9/24
CPC classification number: H01B1/02 , B81B2201/0221 , B81B2203/04 , B81C1/00666 , B81C1/00698 , B81C2201/017 , B81C2201/0181 , C23C14/025 , C23C14/165 , C23C14/34 , H01G4/33 , H01G5/16 , H03H9/131 , H03H9/173 , H03H9/2457 , H03H2003/021 , H03H2003/0428 , H03H2009/02291
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公开(公告)号：EP1712515A3
公开(公告)日：2011-09-14
申请号：EP06075741.6
申请日：2006-03-30
Applicant: Delphi Technologies, Inc.
Inventor： Chilcott, Dan W.
IPC: B81B3/00
CPC classification number: B81B3/0072 , B81B2201/0235 , B81B2201/0242 , B81B2201/0264 , B81B2203/0315 , B81B2203/0338 , B81C2201/0135 , B81C2201/014 , B81C2201/017
Abstract: A technique (400) for manufacturing a micro-electro mechanical structure includes a number of steps. Initially, a cavity is formed into a first side of a handling wafer (404), with a sidewall of the cavity forming a first angle greater than about 54.7 degrees with respect to a first side of the handling wafer at an opening of the cavity. Then, a bulk etch is performed on the first side of the handling wafer to modify the sidewall of the cavity to a second angle greater than about 90 degrees (406), with respect to the first side of the handling wafer at the opening of the cavity. Next, a second side of a second wafer is bonded to the first side of the handling wafer (408).
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公开(公告)号：EP2019080A3
公开(公告)日：2011-03-09
申请号：EP08160899.4
申请日：2008-07-22
Applicant: Dalsa Semiconductor Inc.
Inventor： Fortin, Vincent , Quellet, Luc
CPC classification number: B81C1/00666 , B81C2201/017 , C23C16/24 , C23C16/56
Abstract: A structural film, typically of silicon, in MEMS or NEMS devices is fabricated by depositing the film in the presence of a gas other than nitrogen, and preferably argon as the carrier gas.
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Patent Agency Ranking
公开(公告)号：EP1461286B1
公开(公告)日：2007-08-08
申请号：EP02716555.4
申请日：2002-05-02
Applicant: Silverbrook Research Pty. Limited
CPC classification number: B81C1/00666 , B81C2201/0167 , B81C2201/017 , C23C14/024 , C23C14/0641 , C30B23/02 , C30B29/38 , C30B29/605
Abstract: A crystalline thin film structure formed by the deposition of a predominant first crystalline material in two or more layers interleaved by layers of a second crystalline material having a lattice constant that differs from the lattice constant of the predominant first crystalline material in order to disrupt the growth of columnar crystals in the predominant first crystalline material in order to reduce the differential stress profile through the thickness of the film structure relative to the differential stress profile of a crystalline thin film structure formed solely from the predominant first crystalline material.
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97.发明授权Method for manufacturing integrated devices including electromechanical microstructures, without residual stress 有权一种用于生产具有机电微结构集成器件过程中，没有残余应力
公开(公告)号：EP1028466B1
公开(公告)日：2006-08-02
申请号：EP99830068.5
申请日：1999-02-09
Applicant: STMicroelectronics S.r.l.
Inventor： Ferrari, Paolo , Vigna, Benedetto , Montanini, Pietro , Castoldi, Laura , Ferrera, Marco
CPC classification number: B81B3/0072 , B81B2203/033 , B81C1/00666 , B81C2201/017 , G01P15/0802 , G01P2015/0828
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公开(公告)号：EP1461286A4
公开(公告)日：2006-01-04
申请号：EP02716555
申请日：2002-05-02
Applicant: SILVERBROOK RES PTY LTD
Inventor： SILVERBROOK KIA
CPC classification number: B81C1/00666 , B81C2201/0167 , B81C2201/017 , C23C14/024 , C23C14/0641 , C30B23/02 , C30B29/38 , C30B29/605
Abstract: A crystalline thin film structure formed by the deposition of a predominant first crystalline material in two or more layers interleaved by layers of a second crystalline material having a lattice constant that differs from the lattice constant of the predominant first crystalline material in order to disrupt the growth of columnar crystals in the predominant first crystalline material in order to reduce the differential stress profile through the thickness of the film structure relative to the differential stress profile of a crystalline thin film structure formed solely from the predominant first crystalline material.
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99.发明公开Method for manufacturing integrated devices including electromechanical microstructures, without residual stress 有权一种用于生产具有机电微结构集成器件过程中，没有残余应力
公开(公告)号：EP1028466A1
公开(公告)日：2000-08-16
申请号：EP99830068.5
申请日：1999-02-09
Applicant: STMicroelectronics S.r.l.
Inventor： Ferrari, Paolo , Vigna, Benedetto , Montanini, Pietro , Castoldi, Laura , Ferrera, Marco
CPC classification number: B81B3/0072 , B81B2203/033 , B81C1/00666 , B81C2201/017 , G01P15/0802 , G01P2015/0828
Abstract: On a substrate (20) of semiconductor material, a sacrificial region (21) is formed and an epitaxial layer (25) is grown; then a stress release trench (31) is formed, surrounding an area (33) of the epitaxial layer (25), where an integrated electromechanical microstructure is to be formed; the wafer (28) is then heat treated, to release residual stress. Subsequently, the stress release trench (31) is filled with a sealing region (34) of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region (34), a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.
Abstract translation: 上的半导体材料的基片（20），牺牲区域（21）被形成和外延层（25）上生长; 外延层（25），其中，在集成式机电微观结构是将要形成的那么应力释放槽（31）形成，周边区域（33）; 晶片（28）进行热处理，以释放残余应力。 接着，应力释放槽（31）中填充有电介质材料制成的密封区域（34），和集成的部件而形成。 最后，通过密封区域（34）包围的区域内，微结构定义沟槽中形成，并且所述牺牲区域被去除，因此，与零张残余应力获得集成微结构。
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100.发明公开Method of fabrication of an infrared radiation detector and more particularly an infrared sensitive bolometer 失效赫斯特伦·弗朗西斯·弗朗西斯·弗朗西斯科·史密斯·德特科
公开(公告)号：EP0867702A2
公开(公告)日：1998-09-30
申请号：EP98870058.9
申请日：1998-03-26
Inventor： Fiorini, Paolo , Sedky, Sherif , Caymax, Matty , Baert, Christiaan
CPC classification number: B81C1/00666 , B81C2201/017 , G01J5/20 , H01L31/09 , H01L31/1804 , Y02E10/547 , Y02P70/521
Abstract: A method of fabricating an infrared sensitive bolometer, comprising the steps of:
forming a sacrificial layer (11, 12 or 43) on a substrate (10 or 41);
patterning said sacrificial layer (11, 12 or 43) ;
depositing or growing a layer (13 or 42) consisting essentially of polycrystalline SiGe on said sacrificial layer;
depositing an infrared absorber (49) on said polycrystalline SiGe layer;
removing the sacrificial layer (11, 12 or 43).Abstract translation: 一种制造红外敏感辐射热计的方法，包括以下步骤：在衬底（10或41）上形成牺牲层（11,12或43）; 图案化所述牺牲层（11,12或43）; 在所述牺牲层上沉积或生长基本上由多晶SiGe组成的层（13或42）; 在所述多晶SiGe层上沉积红外吸收体（49）; 去除牺牲层（11,12或43）。
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