公开(公告)号：US2988516A

公开(公告)日：1961-06-13

申请号：US79934559

申请日：1959-03-13

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIGERU KAMIYA

IPC: C09K11/67

CPC classification number: C09K11/678

公开(公告)号：US6433285B2

公开(公告)日：2002-08-13

申请号：US73579200

申请日：2000-12-14

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： MAEDA KENJI ,  TAKATA TAKASHI ,  NARAOKA HIROKI ,  HOMMA HAJIME ,  NONOYAMA SHIGERU ,  ARAI YOSHIYUKI ,  YAMADA YUICHIRO ,  ITO FUMITO

IPC: G06K19/077 ,  H01L21/56 ,  H01L23/498 ,  H05K3/28 ,  H05K1/16

CPC classification number: G06K19/072 ,  G06K19/07743 ,  G06K19/07745 ,  H01L21/565 ,  H01L23/49855 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/284 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a printed wiring board, an IC card module including the printed wiring board, and a method for fabricating the IC card module, for improving reliability of IC cards. The printed wiring board and the IC card module of the invention include: a base having a resin sealing region, clamped regions in a periphery zone of the resin sealing region clamped with a sealing mold, and non-clamped regions in the periphery zone; and terminals for external connection formed on the top surface of the base. The terminals are formed in a region other than any of the resin sealing region, the clamped regions, and the non-claimed regions.

Abstract translation: 本发明提供一种印刷电路板，包括印刷电路板的IC卡模块以及用于提高IC卡的可靠性的IC卡模块的制造方法。 本发明的印刷线路板和IC卡模块包括：具有树脂密封区域的基座，用密封模具夹持的树脂密封区域的周边区域中的夹持区域和周边区域中的非夹紧区域; 以及形成在基座顶表面上的用于外部连接的端子。 端子形成在除了树脂密封区域，夹紧区域和非索赔区域中的任何一个以外的区域中。

公开(公告)号：US3911262A

公开(公告)日：1975-10-07

申请号：US45239374

申请日：1974-03-18

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： IZUMI YOSHIHIRO ,  KAWASAKI TATSUO

IPC: G06F3/147 ,  G06F3/14 ,  G06K15/18

CPC classification number: G06F3/1407

Abstract: A decimal point display circuit for use in an electronic desktop calculator, etc. which displays the result of a calculation or an entry number from the higher digits when it exceeds the number of digits in the numerical display, and displays the number of digits above the decimal point but not displayed in the numerical display by a digit mark in the numerical display. Even when the number of digits of the result of a calculation or an entry number exceeds the number of digits in the numerical display, it can be displayed in such a manner that the digits in the numerical display serve as the effective digits.

Abstract translation: 用于电子桌面计算器等的小数点显示电路，当超过数字显示中的位数时，从较高数字显示计算结果或输入号码，并显示位数 高于小数点，但数字显示中不显示数字显示。 即使当计算结果或输入数字的数字的数量超过数字显示中的位数时，也可以以数字显示中的数字作为有效数字的方式显示。

公开(公告)号：US3887827A

公开(公告)日：1975-06-03

申请号：US40853173

申请日：1973-10-23

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KATAYAMA MITSUMASA

IPC: H01J29/02 ,  H01J31/38

CPC classification number: H01J29/02

Abstract: A target assembly of an image pick-up tube is provided which includes a stepped annular support member for a target substrate secured between a face plate and a front end portion of a tubular envelope of the image pick-up tube. The target substrate is affixed within the outwardly offset portion of the support member. The support member enables a fabrication sequence to be used which obviates exposure of the target substrate to mechanical or thermal shock during manufacture, permits the affixing material to be out of the field of view in a straightsides image pick-up tube, and furnishes automatically accurate centering of the target substrate. In combination with a softmetal sealing ring having an annular width extending from the inwardly offset portion of the support member to the inner side of a signal ring capping the face plate and the envelope, the support member also insulates the target substrate from mechanical shock during use of the image pick-up tube.

Abstract translation: 提供了一种图像拾取管的目标组件，其包括固定在图像拾取管的管状外壳的面板和前端部之间的目标基板的阶梯状环形支撑构件。 目标衬底固定在支撑构件的向外偏移部分内。 支撑构件使得能够使用制造顺序，其可以避免在制造期间目标衬底暴露于机械或热冲击，允许固定材料在直视图像拾取管中超出视场，并且提供 自动精确定位目标基板。 与具有从支撑构件的向内偏移部分延伸到覆盖面板和封套的信号环的内侧的环形宽度的软金属密封环组合，支撑构件还使目标衬底不受机械冲击 在使用图像拾取管时。

公开(公告)号：US3879837A

公开(公告)日：1975-04-29

申请号：US44367074

申请日：1974-02-19

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： MIZUKOSHI KANJI ,  ANDOU MINORU ,  OKUNO HISAO

IPC: B23K1/20 ,  B23K3/08 ,  H01L21/00 ,  H01L21/60 ,  B23K31/02

CPC classification number: H01L21/00 ,  B23K1/20 ,  B23K3/087 ,  B23K2201/40 ,  H01L24/31 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A method of soldering a semiconductor plate to a metal substrate comprising the steps of disposing or supplying solder at that portion of the metal substrate which is remote from the portion to be soldered with the semiconductor plate, and supplying the melted solder to the soldering portion of said semiconductor plate and said metal substrate through a groove provided in said metal substrate and extending from said remote portion to said soldering portion.

Abstract translation: 一种将半导体板焊接到金属基板的方法，包括以下步骤：在远离待与半导体板焊接的部分的金属基板的该部分处设置或供应焊料，并将熔融的焊料供应到 所述半导体板和所述金属基板通过设置在所述金属基板中并从所述远端部分延伸到所述焊接部分的凹槽。

公开(公告)号：US3874955A

公开(公告)日：1975-04-01

申请号：US34149373

申请日：1973-03-15

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA SHIGERU

IPC: H01L21/82 ,  H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L29/00 ,  H01L7/44 ,  B01J17/00 ,  H01L27/10

CPC classification number: H01L23/535 ,  H01L21/82 ,  H01L27/0733 ,  H01L27/112 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/053 ,  Y10S148/122 ,  H01L2924/00

Abstract: A method of manufacturing an MOS integrated circuit by utilizing a self-alignment technique is provided, wherein a capacitor is fabricated independently of other circuit elements. The capacitor is composed of a preliminary diffused region, a silicon dioxide layer and a gate electrode section having at least a portion thereof laid on top of the preliminary diffused region. The capacitor produced in accordance with this method is positively separated from other circuit elements and it may be used, for example, as an auxiliary storage capacitor for an inverter circuit to prevent the lowering of the output signal.

公开(公告)号：US3772463A

公开(公告)日：1973-11-13

申请号：US3772463D

申请日：1972-02-24

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： WAKAI S ,  SUGANO H

IPC: H04N9/68 ,  H04N9/71 ,  H04N9/48

CPC classification number: H04N9/71 ,  H04N9/68

Abstract: A chrominance amplifier circuit, adapted to be formed in a monolithic integrated circuit, in which an automatic gain control function is performed by a circuit arrangement containing no capacitor, the automatic gain control function having no influence on the bandwidth characteristic of the amplifier so that the chrominance amplification operation can be stably performed.

Abstract translation: 一种色度放大器电路，适于形成在单片集成电路中，其中通过不含电容器的电路装置执行自动增益控制功能，所述自动增益控制功能对放大器的带宽特性没有影响， 可以稳定地进行色度放大操作。

公开(公告)号：US3753711A

公开(公告)日：1973-08-21

申请号：US3753711D

申请日：1971-12-13

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KOBAYASHI Y ,  YAKENO K

IPC: H01J9/227 ,  G03C5/00

CPC classification number: H01J9/2271

Abstract: A phosphor screen for color picture tube is usually produced by the first step which comprises suspending a blue emission phosphor in an aqueous solution of photo-setting photosensitive material comprising polyvinyl alcohol and ammonium dichromate, applying thus obtained suspension to inner surface of face panel to form a photosensitive film, exposing said film through apertures of shadow mask and developing the exposed film to form dotty phosphor film and the second and the third steps of forming the dotty phosphor films of green and red emissions in this order by substantially the same procedure as that of the first step. According to the present invention, the dotty phosphor films formed at said first and second steps are treated with chromic acid solution to harden said films, whereby color mixing, namely, so-called color fogging caused by a phosphor of other color emission used at the subsequent step is reduced and color purity of emission from phosphor screen face is improved.

Abstract translation: 彩色显像管荧光屏通常是通过第一步产生的，其中包括将蓝色荧光体悬浮在包含聚乙烯醇和重铬酸铵的光固化感光材料的水溶液中，将得到的悬浮液涂在面板的内表面上以形成 感光膜，通过荫罩的孔露出所述膜，并显影曝光的膜以形成点状荧光膜，第二和第三步骤按照与该步骤基本相同的程序按顺序形成绿色和红色发射的点状荧光膜 的第一步。 根据本发明，在所述第一和第二步骤中形成的点状荧光体膜用铬酸溶液处理以使所述膜硬化，由此颜色混合，即由在其中使用的其它颜色发射的荧光体引起的所谓的着色 随后的步骤减少，荧光屏面的发射色纯度提高。

公开(公告)号：US3746950A

公开(公告)日：1973-07-17

申请号：US3746950D

申请日：1969-08-15

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAWAKI T ,  FUJIWARA S ,  HASEGAWA H ,  KANO G ,  IIZUKA M

IPC: H01L29/00 ,  H03F1/30 ,  H03F1/34 ,  H03F3/183 ,  H04R23/00 ,  H01L11/00 ,  H01L15/00

CPC classification number: H04R23/006 ,  H01L29/00 ,  H03F1/302 ,  H03F1/34 ,  H03F3/183

Abstract: A pressure-sensitive semi-conductor device with a Schottky barrier in which a separation space is formed underneath the insulating film covering a major surface portion of the semiconductor substrate and disposed adjacent a metal layer received in a recess in the substrate and extending through an opening in the insulating film, whereby the input pressure is applied to the metal layer. The separation space is formed by side-etching with the insulating film serving as mask.

Abstract translation: 一种具有肖特基势垒的压敏半导体器件，其中在覆盖半导体衬底的主表面部分的绝缘膜的下方形成分隔空间，并且设置在容纳在衬底的凹部中的金属层附近并延伸穿过 在绝缘膜上形成开口，由此将输入压力施加到金属层。 通过用作为掩模的绝缘膜进行侧面蚀刻来形成分离空​​间。

公开(公告)号：US3729807A

公开(公告)日：1973-05-01

申请号：US3729807D

申请日：1971-10-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJIWARA S

IPC: H01L21/00 ,  H01L21/607 ,  B23K31/02

CPC classification number: H01L21/00 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/4823 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83444 ,  H01L2224/83805 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01063 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/15312 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/01031 ,  H01L2924/2011 ,  H01L2924/01052

Abstract: In making a semiconductor device comprising a die of silicon, germanium or gallium arsenide, the bonding of the die onto a metal header (i.e., holding member) is made firmly without insertion of a conventional thin gold film therebetween, by depositing gold onto the bonding face of a slice, which is to be cut into the die, in such a manner that at least the surface of the deposited layer is gold or an alloy of gold containing small amounts of an additive.

Abstract translation: 在制造包括硅，锗或砷化镓的裸片的半导体器件中，通过将金沉积到键合上，将裸片与金属接头（即，保持构件）的接合牢固地制成，而不会在其间插入常规的薄金膜 要切割成模具的切片的面，至少沉积层的表面是金或含有少量添加剂的金的合金。